So I want to program a PAL device as a Hex-to-7-Segment Display (for academic reasons and connecting with the distant-past
Reading Chapter 8 - Karnaugh Mapping, I came across the following statement.

"The SOP solution is usually better if using the TTL logic family, as NAND gates are the basic building block, which works well with SOP implementations. On the other hand, A POS solution would be acceptable when using the CMOS logic family since all sizes of NOR gates are available."

I'm still unclear why one would use SOP over POS, generally speaking. Also, why is SOP better for TTL logic if I'm going to program a PAL.

 

The basic circuit to implement an SOP solution involves an AND gate for each product with the outputs of all of those feeding a single OR gate for the final sum. But those can all be replaced by NAND gates. Do you understand why?

Now consider a POS solution that involves an OR gate for each sum with those feeding a single AND gate for the final product. What type of gate can all of those be replaced with?

I'm not an expert on the subtleties of TTL implementations, but I think that it is easier to provide multi-input NAND gates than it is NOR gates in TTL. In CMOS it is pretty much the same (the NAND has a slight edge).

 

I'm a bit lost on "The basic circuit to implement an SOP solution involves an AND gate for each product with the outputs of all of those feeding a single OR gate for the final sum. But those can all be replaced by NAND gates. Do you understand why?"

 

An SOP equation would be of the form

Y = A'C + AB' + BC'

Note that this is made up on the fly and I'm not going to even look to see if it can be reduced.

So to implement this, we need three two-input AND gates for each term and then a three-input OR gate to combine the outputs of the AND gates to get Y. I'm assuming that both the straight and complemented versions of all the input variables are available. If not, we also need some NOT gates.

Using DeMorgan's Theorem, we can replace the OR gate with a NAND gate provided we also invert all of the inputs. But we can incorporate those inversions into the AND gates that precede them by simply making them NAND gates.

 

Regarding the conversion methodology from straight AND and OR gates (and NOT) to NAND that makes sense, but what's the advantage of using NAND gates to implement this?

I was reading Beboop to the Boolean Boogie, and Maxfield mention that NAND gates use less transistors (advantage). Maybe it's optimizing the usage of 74xx00 chips, so you're not wasting unneeded pins using 74xx08, 74xx04, 74xx32

I appreciate you helping a newbie through this...

 

Regarding the conversion methodology from straight AND and OR gates (and NOT) to NAND that makes sense, but what's the advantage of using NAND gates to implement this?

I was reading Beboop to the Boolean Boogie, and Maxfield mention that NAND gates use less transistors (advantage). Maybe it's optimizing the usage of 74xx00 chips, so you're not wasting unneeded pins using 74xx08, 74xx04, 74xx32

I appreciate you helping a newbie through this...

I already addressed this. To elaborate, in TTL the basic building block is the NAND gate because of it's simpler construction -- it can use multi-emitter transistors and thus take up less room and be faster. In CMOS it's pretty much a toss-up thought in well-matched CMOS, the NAND still has the advantage over the NOR.

It has nothing to do with optimizing the use of a particular discrete logic chip -- especially when it appears to be focusing on PLDs and such.