Dear Power Electronic community,

As most of nowadays engineer I tend to use simulation to accelerate design of power supply, espacially to derive the MOSFETs switching behaviour to determine losses for heatsink design.
My question concerne the PSpice model of IPA60R170CFD7 (.lib in attachment) provided by Infinéon which is supposed to be working with LTSpice. But my simulation stop very quickly because of time step too small. I believe this is a lack of robustness or something but when regarding more in detail the subcircuit, I can see that the "capacitor part of MOSFET" seems to be out of the semiconductor part : see the .SUBCKT cool_tech part at the beginning.

I created the symbol with automatic generation (right click on the subcircuit part : .SUBCKT IPA60R170CFD7_L1 drain gate source)

I come to my question : How can I build/create a component which is working properly with my simulation. The simulation is a double pulse test. I can say my simulation is working with other components like the nmos (I tried just now with de STP8NM60 in the librairie, and my simulation is correct)

In attachment you will find the .lib file and the simulation file

Thank you in advance for your help
Maximin

 

I recommend that you also post to the LTSpice users group. Helmut and Alex (Bordodynov) are extremely knowledgeable about such matters, Alex also frequents this site @Bordodynov Maybr he will notice the shoutout. My experience is that SPICE models from all kinds of sources will run if they contain no syntax errors. The results may or may not match actual devices. I know that for the Power BJT -- TIP31C there are no less than 13 different models that produce a variety of interesting results. There is very little in the way of design verification for old parts and old models.

 

I made a correction to the factory models.
For example, I set the parasitic inductances to Rser=0. By default, Rser=1m, which can make a large error. I have also set some options.

 

Thank you for your answer,
I included your modifications in my simulation file and it seems to be OK

From your point of view, is there any explanation about the fact that capacitive behaviour is dissociated from the rest of the model ? And this part seems the same shared for all references which is, in my opinion, not the reality. I have just understood that the subcircuit IPW60R031CFD7_L1 is relink to cool-tech_L1 parameter with the line (I guess) :
"X1 dd g s cool_tech_L1 PARAMS:...."

Do you have any tips or links to usefull lessons to help me understand how the simulations parameter impact the way of simulation because is seems to be very important for convergence of simulation.

Your help is very appreciated.
Maximin