# Up/down Decade counter using D Flipflop

#### MrChips

Joined Oct 2, 2009
23,090
The purpose of the Karnaugh map in a synchronous sequential circuit design is to pictorially identify all the possible conditions that will result in the flip-flop assuming a 1-state on the next clock pulse.

We take advantage of all non-existent states (since they don't exist and therefore don't matter) in order to simplify the boolean logic solution.

Karnaugh maps are also useful in preventing race problems. (This has nothing to do with racial tension in human society). Here is the solution for the A flip-flop. (In this exercise, we assume that flip-flop A represents the least significant bit in the 4-bit BCD counter.)

We group all the 1s and Xs in the largest group possible, of eight's, four's or two's, remembering that the map wraps around an imaginary cylinder both horizontally and vertically.

It is ok to include the same square in more than one group.
In fact, when groups share a common square or squares, that is, when all groups overlap, this will ensure that race problems are eliminated.

In this example, the result is a single group of eight squares represented by the boolean A' (i.e. NOT A).

This result is intuitive for the least-significant bit A. That is, the A flip-flop toggles on every clock pulse.

Last edited:
• anhnha
Thread Starter

#### fordelon1

Joined Aug 16, 2011
13
B=d'b'a+ba'+da'
c=c'ba+cb'+ca'
d=cba+da'

#### MrChips

Joined Oct 2, 2009
23,090
B is incorrect.
C and D are correct.
You're getting the hang of it.

Can you show your maps so that others can see how you arrived at your answers?

Thread Starter

#### fordelon1

Joined Aug 16, 2011
13
I do have a deadline for this sir, tomorrow afternoon...
well anyways, thank you for your effort in answering my question..
I'm out of time ..

Thread Starter

#### fordelon1

Joined Aug 16, 2011
13
maybe you can help me w/ the schematic diagram sir..
need it badly #### MrChips

Joined Oct 2, 2009
23,090
Here is the final wrap-up of this tutorial for completeness.

To recap, we are designing a synchronous 0-9 counter using the principle of finite state machines.

We will choose any type of flip-flop in the design, S-R, D, J-K or T-type flip-flop.

Step 1 - Draw the truth-table showing the current state and the next state. Include all unused states as "don't cares".

Step 2 - Draw the Karnaugh map for each flip-flip.

Step 3 - Extract from each Karnaugh map the boolean expression that will result in a logic 1 output, taking into account "don't care states". Keep Q and Q' terms separate.

Step 4 - Implement the combinational logic with respect to the type of flip-flop used.

In our example, we arrive at the four equations for four flip-flops.

QA = A'(1) + A(0)
QB = B'(AD') + B(A')
QC = C'(AB) + C(A' + B')
QD = D'(ABC) + D(A')

Now we apply this to the equation of the type of flip-flop used.

S-R Flip-Flop
Q(next) = S + R'Q

J-K Flip-Flop

Q(next) = JQ' + K'Q

D-type Flip-Flop

Q(next) = D

T-type Flip-Flop

Q(next) = TQ' + T'Q

As an example, suppose we are using J-K flip-flops in our solution,

for QA flip-flop, J = 1, K = 1

for QB flip-flop, J = AD', K = A

for QC flip-flop, J = AB, K = (A' + B')' = AB

for QD flip-flop, J = ABC, K = A