Hello Experts,
I have 2 SiC mosfets connected in a half bridge configuration.
Let call the top mosfet Q1 and the bottom mosfet Q2.

In parallel to this I have another half bridge connected in parallel.
Let call the top mosfet Q3 and the bottom mosfet Q4.

The Drain of Q1 and Q3 are shorted.
The Source of Q2 and Q4 are shorted.
The Source of Q1 is shorted to the Drain of Q2.
The Source of Q3 is shorted to the Drain of Q4.

And I have a resistive load connected at the midpoint of these 2 half bridges in between them.

I have a voltage source(Lets call this V1) connected as follows:
The positive terminal of the V1 goes to the drain of Q1 and Q3.
The negative terminal of the V1 goes to the drain of Q3 and Q4.
There is a capacitor bank in parallel.

At any time Either Q1,Q4 are turned OR Q3,Q2 are turned on.

The gate voltage given to these mosfets are (+15, -5).

With the above setup:
I am facing a weird issue, If V1 is disconnected and neither Q1,Q4 or Q3,Q2 are turned on,
if I measure across V1(across the H bridge), I measure about 20 to 22v? Why is this. Should it not be 0v?

PS: When posting this question to an AI chat bot , I got this reply below, Could you experts confirm this:

This voltage reading across V1 when neither Q1,Q4 or Q3,Q2 are turned on is likely due to the parasitic capacitances in the circuit.

When the MOSFETs are off, there is no current flowing through the resistive load, so any voltage on the parasitic capacitances can persist. The capacitances are charged to the voltage level of the previous switching cycle. When the voltage source V1 is disconnected, the voltage level on the parasitic capacitances is not discharged, and can be read as a voltage across V1.

To mitigate this issue, you can try to discharge the parasitic capacitances by shorting the output terminals of the half-bridge to ground or a neutral point (e.g. the midpoint of the two half-bridges) before measuring the voltage across V1. Another approach is to use snubber circuits to reduce the voltage transients and mitigate the effects of parasitic capacitances.

 

Post a schematic.

 

The only way I could understand that from you lengthy description is to draw a schematic.
But since that's your job, not mine, please supply one.

 

What did you measure it with? Was it a multimeter with 10MΩ input resistance? I imagine that the supply voltage is quite high (otherwise no need for SiC).
If so, you might be measuring the leakage due to dirt on the pcb.

 

I dont have a full fledged schematic yet, as i am using a few evaluation pcbs together.
But here is a basic jest of the schematic that i was able to draw in LTspice. I know its very crude, but if there is any missing information needed , please let me know, i can physically measure them if required..


Edit: Added the load resistors and voltage balancing resistors

 

What did you measure it with? Was it a multimeter with 10MΩ input resistance? I imagine that the supply voltage is quite high (otherwise no need for SiC).
If so, you might be measuring the leakage due to dirt on the pcb.

Yes measured with a multimeter, input resistance above 20 Mohm , also measures it with a oscilloscope with the same result. I was suspecting if the 20v developed is some high frequency component, but it turned out to be pure DC.
Regarding SiC, we had a few spares and wanted to use them.

 

we had a few spares and wanted to use them.

Do you really have Q1 Gate tied to Q4 Gate? and Q2 Gate tied to G3? You will not have spare parts for long.
,
Maybe you are turning on Q1 and Q4 at the same time, using different gate drivers.

As for developing a 20V dc voltage: are you driving the gates when you make the measurements? Could the voltage be peak rectifying the Gate waveform.

RonS.

 

Do you really have Q1 Gate tied to Q4 Gate? and Q2 Gate tied to G3? You will not have spare parts for long.
View attachment 291391,
Maybe you are turning on Q1 and Q4 at the same time, using different gate drivers.

As for developing a 20V dc voltage: are you driving the gates when you make the measurements? Could the voltage be peak rectifying the Gate waveform.

RonS.

Yes we have 4 individual gate drivers. i just wanted to illustrate that so to let you guys know q1 and q4 are turned on at the same time.
I am using 4 of these evaluation PCBs "https://www.ti.com/tool/UCC21710QDWEVM-025" as my gate drivers

To answer your second question, let me explain the sequence here
1. My gate drivers are powered on and gate voltage is -5 by default
2. I close my MCB so the H bridge sees 60 v
3. From a MCU i , instruct the gates drivers of Q1& Q4 to switch on at 10% duty cycle. I see a that V1 consumes about 220mA at this point. I also see a pulsed 0 to 60 wave arcoss the load resistor R1.
4. From a MCU i , instruct the gates drivers of Q1& Q4 to switch off. Here i see that V1 now consumes 0 Amps and there is no pulsed wave across the load any more. So I know that my Mosfets are really switch off.
5.I open the MCB, here the voltage drop across the H bridge reduces slowly from 60 v....(The capacitor bank discharges via R2,R3) and reduces to about 20v. It doesn't go below 20 volts!!!

 

20V across 100k load. I think the MCB leaks that much current. If you add in a 10k bleader, across the caps does the voltage drop to 2V?

 

Hi @ronsimpson , We tried reducing the bleader, but results in the same.
Infact I removed the DC bus altogether , just to check (C1, R2, and R3) and I still get 20 v across the bus

I am beginning to suspect by gate driver now !!