input A(8 bits)-> two's complement
input B(8 bits)-> two's complement
output F(8bits)--> F= A times B;

How can I design an two's complement multiplier using 4bit full adder, decoder, mux, logic gates.

The goal is to design an 8bit ALU and one of the functions that it must performs is A times B.
So, I'm doing 1bit ALU'S and linking everything. But How can I do that?
I saw sth about Baugh-Wooley with 4bit, but How can I design it with 8 bits?

 

I would take the absolute value of both operands and latch the signs of the operands.
Then I would divide each of the positive operands into two bit groups.
For each of the four 2-bit groups in the multiplier form a 16-bit partial product from a shifted version of the multiplicand
Add the four, 16-bit partial products
Apply the sign from the latched sign bits of the operands.

 

The last time I checked (8 bits) * (8 bits) = (16 bits)