the ac input Z calculation is very similar to the dc input Z calculation, with the exception that under high enough frequency, Re1 is shorted and Re2 is shorted for ac purposes.

so your input impedance will just be the divider resistors + the beta amplified Re resistors (for ac purposes), all in parallel.

What is the point of this post? This is exactly what tnk already described in post #3.

 

I can give you a quicker approach.

all that transistor does here for DC purposes is to "amplify" the Re resistors and present them as a much larger resistor than they really are, by (1+beta) times.

so, all you do is to parallel (1+beta)*Re to the lower resistor in the divider and then calculate Vb that way.

by my calculation, it yields a Vb of 2.38v, vs. 2.41v for the first stage, calculated by my spreadsheet, for an error rate of 1.4%. Ie is then (2.41-0.7)/1868=.9ma.

the above calculation doesn't factor in the "equivalent" resistance from the b-e junction: 0.7v/0.9ma=778ohm (in terms of emitter current). so to do a 2nd order correction, you add the 778ohm to the Re resistance of 1868, you get the equivalent resistance of (1+200)*(778+1968)=531,846ohm, and Vb=2.4149v, vs. the real thing of 2.4142v, and an error rate of 0.028%.

all that, without killing yourself.

Your method doesn't seem to me to be any quicker.

I don't find the small amount of algebra to be a killing experience, but for those who do, these two equations:

1. Vb=Vth-Rth*Ib

2. Vb=Vbe+(1+hfe)*Ib*RE

can be solved symbolically, yielding two formulas:

R1 and R2 are the bias divider resistors, RE is the DC resistance seen by the emitter current, and Vcc is the supply voltage feeding the top resistor of the bias divider.

\(Ie=(1+\beta)\frac{R2*Vcc-Vbe*(R1+R2)}{RE*(1+\beta)*(R1+R2)+R1*R2}\)

\(Vb=\frac{R2*(R1*Vbe+RE*Vcc*(1+\beta))}{RE*R2*(1+ \beta)+R1*(R2+RE*(1+\beta))}\)

These two formulas give the exact solution taking into account the effect of the base current on the bias divider, without any need for further correction.

 

Hi Millwood,

It's interesting to try your method with your lower limit hfe stipulation of 50 - for stage 1 for instance.

The first estimate for Vb = 2.09 V giving Ie = 743uA

Using your 2nd adjustment approach gives Vb = 2.21 V which is close to what I obtained with my method without an additional iteration.

Using your method with hfe=50, there is an error in your first estimate of around 5.4%.

In fact it takes me longer to use your technique than mine, but I guess it's the method one is familiar that tends to be the easiest.

Neither method killed me by the way.

Thanks for your insights.

 

Hi Millwood,

It's interesting to try your method with your lower limit hfe stipulation of 50 - for stage 1 for instance.

The first estimate for Vb = 2.09 V giving Ie = 743uA

Using your 2nd adjustment approach gives Vb = 2.21 V which is close to what I obtained with my method without an additional iteration.

the right Vbe=1.92v for the 1st stage, assuming beta=50.

ignoring Ib, you get Vbe=2.5v. error rate: 30%

using the beta-amplified Re approach, you get Vbe=1.69v, error rate: 12%

using the Vbe-equivalent Re approach, you get Vbe=1.95v, error rate: 2%.

the cause for the error is basically the size of Ib vs. the current going through the divider network. Lower beta or higher divider resistance means higher Ib vs. the divider current, thus higher error rate.

Using your method with hfe=50, there is an error in your first estimate of around 5.4%.

that doesn't look right to me.

 

You've done these calculations with a beta of 20, not 50

the right Vbe=1.92v for the 1st stage, assuming beta=50.

ignoring Ib, you get Vbe=2.5v. error rate: 30%

using the beta-amplified Re approach, you get Vbe=1.69v, error rate: 12%

using the Vbe-equivalent Re approach, you get Vbe=1.95v, error rate: 2%.

Using your method with hfe=50, there is an error in your first estimate of around 5.4%.

that doesn't look right to me.

That's because you used a beta of 20, whereas tnk used 50.