In 2007 KMoffet posted a circuit for producing two pulses from rising and falling edge of 5v logic signal (see attached). It works (very well) with 5v supply, 5v output and 5V signal. I would like to run it with 12v supply, 12v output and 5V signal. I am currently able to do this with transistor circuit upping the 5v signal to 12v.

I am not skilled with circuit design and I wonder what is best way of doing this.

Alan

 

hi Alan,
The 4093 will work OK at 12V, the timing may need a small adjustment.
E
d/s Clip:
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground).

 

In 2007 KMoffet posted a circuit for producing two pulses from rising and falling edge of 5v logic signal (see attached). It works (very well) with 5v supply, 5v output and 5V signal. I would like to run it with 12v supply, 12v output and 5V signal. I am currently able to do this with transistor circuit upping the 5v signal to 12v.

I am not skilled with circuit design and I wonder what is best way of doing this.

Alan

Sorry my fault for not framing query more clearly but what I was really after was if you run circuit at 12v what is best way to handle the incoming 5v signal as 5v signal into 12 v circuit did not work.

 

Convert the 5V signal to 12V using a transistor, something like this:

 

Sorry my fault for not framing query more clearly but what I was really after was if you run circuit at 12v what is best way to handle the incoming 5v signal as 5v signal into 12 v circuit did not work.

Thanks that's is similar to what I came up with so that I have 12v signal & 12v supply.

What are the limitations on inputs into 4093 gates, do they need to be within so many volts of one another to register as two positives? Or is it enough for both of them just to be positive?

 

Logic threshold voltage on CMOS devices is ½VDD, hence 6V for VDD = 12V.

 

The 4.7K pullup (your R2) will not work well with the 1 K input resistor (his R1).

In the original schematic, two of the gates are merely output inverters. They are not necessary to the circuit, and this was a way to tie them off.

Delete R1.
Use the circuit in post #4 to drive one gate connected as an inverter.
Use that inverter's output to drive the two pulse circuits.
Isolate the remaining gate, tie both of its inputs to GND, and leave its output floating.

This is the minimal approach. Note - it changes the output pulse polarity. Both output pulses now are negative-going. If this is a problem, it is easily fixed by re-arranging the two R-C networks. Connect the lower end of R2 to +12 V, and the upper end of R3 to GND.

ak

 

Logic threshold voltage on CMOS devices is ½VDD, hence 6V for VDD = 12V.

The CD4093 has hysteretic input stages, so there are two different transition levels depending on the edge direction. The voltage levels are not tightly controlled, but they are minimally specified in the datasheet.

ak

 

hi Alan,
The original diagram is incorrect.
The High going short pulse on the falling edge of the Vin pulse, is on the output pin #4...
pin#11 gives a Low going pulse.

E

 

hi Alan,
So repurpose the CD4093 [lower right Gate, pins 11,12, & 13] to build this circuit and add the low-cost level shifter transistor.
E

 

The CD4093 has hysteretic input stages, so there are two different transition levels depending on the edge direction. The voltage levels are not tightly controlled, but they are minimally specified in the datasheet.

ak

 

The High going short pulse on the falling edg

hi Alan,
The original diagram is incorrect.
The High going short pulse on the falling edge of the Vin pulse, is on the output pin #4...
pin#11 gives a Low going pulse.

E

 

Thanks Eric I will give your circuit a go.

 

hi Alan,
Let's know how it goes and if you require any modifications.
E

 

Thanks to all for responses and info. Eric used your circuit and everything works fine.