I am trying to design a 555 timer circuit which which is high for 1 second and then low for 20-25ms. I used several calculators online to check my numbers and I got that R1 should be 30k, R2 750, and C 47uF. I built the circuit but I am seeing something strange in the simulation. When started, the output is high at 5V (correct), but then it stays high for ~1.6 seconds. Afterwards it drops to 0V and stays low of ~23ms (also good) but then it rises to only 500mV. I checked my circuit against other examples online but I am not sure what I am doing wrong here. I tried the simulation with both 5V and 12V and the result was the same (except with 12V the output when up to 1.2V instead of 12V). If I let the simulation keep running than it varies between 500mV/0V or 1.2V/0V (depending on the supply)

Can anyone provide some guidance on what I am doing wrong?

 

Hmmm...

The design produces a square wave very close to 100% duty cycle. The recommended min value for the 750 ohm resistor
is 3K.

What is this used for?

 

Hmmm...

The design produces a square wave very close to 100% duty cycle. The recommended min value for the 750 ohm resistor
is 3K.

What is this used for?

The circuit I am (trying) to design it so count pulses from a fan. The fan TACH signal will be hooked up to two binary counters. I am trying to use the 555 so that it has a 1 second high time, which is when one of the counter is counting, and then when it goes low, the signal is switched to a second counter while the data is read from the first counter. This is why I want a high signal for a much longer time than the low signal

I tried some additional simulations with different values and it seems like the first pulse last about +.5 second longer and then starts working. For example, with 430k, 3k, and 3.3uF I see that the initial high time is about 1.5 seconds, then it goes low for ~6.8mS, and then high for 0.99 seconds, and repeats. Is this something normal with the 555 that the initial HIGH period is longer than the regular running cycles or maybe this is some issue with the simulation "stabilizing"?

I think those values though (430k, 3k, and 3.3uF) are going to be the closest I can get to a 1 second HIGH/short low. Considering it is only off by 1.00%, it should be sufficient for calculating the fan speed. And 6.mS should be more than enough time to latch the data and clock it out since the shift register works on the order of nanoseconds.

 

Is this something normal with the 555 that the initial HIGH period is longer than the regular running cycles

Yes. In the first cycle the timing cap has to charge from 0V to 2Vcc/3. In later cycles it charges from Vcc/3 to 2Vcc/3.

 

Is this something normal with the 555 that the initial HIGH period is longer than the regular running cycles or maybe this is some issue with the simulation

That is normal.
The timing capacitor starts at 0V for the first period but then is discharged to 1/3 of the the supply voltage (as determined by the TRIG threshold) for the subsequent cycles (see LTspice top sim below):
If you want to change that so the longer period is the initial negative pulse, you can connect the timing capacitor to the supply voltage instead of ground (see bottom sim).

I see nothing wrong with the circuit.
Perhaps there's a problem with your 555 model.

 

I built the circuit but I am seeing something strange in the simulation. When started, the output is high at 5V (correct), but then it stays high for ~1.6 seconds. Afterwards it drops to 0V and stays low of ~23ms (also good) but then it rises to only 500mV.

That's normal behavior because the capacitor charges from 0V on the first cycle, not 1/3 Vcc.

I tried the simulation with both 5V and 12V and the result was the same (except with 12V the output when up to 1.2V instead of 12V).

The trigger and threshold voltages are ratios of Vcc, so changing supply voltage doesn't affect operation.

If your circuit can't tolerate the longer period on the first pulse, there are ways to address it.

Your circuit is simple, but the schematic could be drawn better. The wire crossing for reset is unnecessary. If you move the decoupling cap on control to the right and down, you can avoid the wire jogs to the timing cap.

I redesigned the timer symbol in Eagle so it makes more sense:

 

I played around with the simulation more and it seems that maybe my timestep was too small. I increased the timestep and even with the 30k/750/47u values, I got very close to what I expected. I calculated a HIGH time of 1.0016s and LOW time of 24.4282mS and the simulation is show 1.008s/27.273mS. This should be more than good for my project since the HIGH time is what really matter as that is when the counting is being done; the LOW time I just need enough time to close the data and since the IC/MCU is working on nanosecond and uSec timescales (respectively), 27ms should be more than good enough

However, I was curious about something you mentioned regarding a minimum value of 3k for R2. I looked over the datasheet and I couldn't find anything that specified this. Is this something just learned from experiencing or is it documented somewhere? Thanks again for the feedback.

 

That is normal.
The timing capacitor starts at 0V for the first period but then is discharged to 1/3 of the the supply voltage (as determined by the TRIG threshold) for the subsequent cycles (see LTspice top sim below):
If you want to change that so the longer period is the initial negative pulse, you can connect the timing capacitor to the supply voltage instead of ground (see bottom sim).

I see nothing wrong with the circuit.
Perhaps there's a problem with your 555 model.



View attachment 309935

I will definitely give that a try. But my understanding what that the capacitor was only supposed to discharged through R2. It seems here that it will discharge between both R1 & R2, no?

 

The circuit I am (trying) to design it so count pulses from a fan. The fan TACH signal will be hooked up to two binary counters. I am trying to use the 555 so that it has a 1 second high time, which is when one of the counter is counting, and then when it goes low, the signal is switched to a second counter while the data is read from the first counter. This is why I want a high signal for a much longer time than the low signal

OK

I tried some additional simulations with different values and it seems like the first pulse last about +.5 second longer and then starts working. For example, with 430k, 3k, and 3.3uF I see that the initial high time is about 1.5 seconds, then it goes low for ~6.8mS, and then high for 0.99 seconds, and repeats. Is this something normal with the 555 that the initial HIGH period is longer than the regular running cycles or maybe this is some issue with the simulation "stabilizing"?

That's normal for a 555 timer.

I think those values though (430k, 3k, and 3.3uF) are going to be the closest I can get to a 1 second HIGH/short low. Considering it is only off by 1.00%, it should be sufficient for calculating the fan speed. And 6.mS should be more than enough time to latch the data and clock it out since the shift register works on the order of nanoseconds.

What is the max frequency of rotation?
Or rather, what is the max tacho output frequency?

 

I played around with the simulation more and it seems that maybe my timestep was too small.

Timestep is a simulation option and has no effect on actual circuit performance.

It seems here that it will discharge between both R1 & R2, no?

The capacitor charges through R1 and R2. It discharges through R2. Since R2 is much much smaller than R1, duty cycle is close to 100%.

 

However, I was curious about something you mentioned regarding a minimum value of 3k for R2. I looked over the datasheet and I couldn't find anything that specified this. Is this something just learned from experiencing or is it documented somewhere? Thanks again for the feedback.

That is the minimum value recommended for an astable timer to ensure startup per app note AN-170.
And something a simulator may or may not show.

 

If you want to change that so the longer period is the initial negative pulse, you can connect the timing capacitor to the supply voltage instead of ground (see bottom sim).

I tried your suggestion but the output seems to vary now. Most of the time it is good but every so often (every 2-3 cycles) it goes low for a full second, before going back high for a second:


Should that be happening? Honestly, the long initial pulse isn't such a big deal since it does stabilize after one or two cycles so that is fine if the count is off for 1 or 2 seconds, just curious though why the unusual cycling is happing. Based on what you mentioned, I though it should start off low and then do the 1sec HIGH/~25ms LOW and stay with that cycling.

 

AN-170.

Thanks, I will check that out.

 

Seems like you should trigger a 555 monostable off the tacho pulses, instead of an astable.
When the pulse is hi->counter 1, when the pulse is low->counter 2

 

I tried your suggestion but the output seems to vary now.

That isn't an astable circuit. The timing cap voltage has to vary between the trigger and threshold voltages. It can't do that in your circuit.

Honestly, the long initial pulse isn't such a big deal since it does stabilize after one or two cycles

It stabilizes after the first charge cycle.

 

Most of the time it is good but every so often (every 2-3 cycles) it goes low for a full second, before going back high for a second:

Don't know why it does that.
May be another simulation anomaly as mine doesn't do that.
Plot the capacitor voltage and see what it does when you see the long pulse.

 

That isn't an astable circuit. The timing cap voltage has to vary between the trigger and threshold voltages. It can't do that in your circuit.

Of course it can.
It's still an astable circuit (did you not see my sim).
The supply voltage is AC ground so, after the initial pulse, it acts the same as if the capacitor were connected to ground.

 

I was curious about something you mentioned regarding a minimum value of 3k for R2. I looked over the datasheet and I couldn't find anything that specified this. Is this something just learned from experiencing or is it documented somewhere?

The discharge transistor is current limited, so there's really no limitation on how small R2 can be.

From Signetics:

Since the discharge transistor also conducts current from R1 (RA in the schematic), you want R1 to be large enough that most of the current in the discharge transistor is from the timing cap.

 

I calculated a HIGH time of 1.0016s and LOW time of 24.4282mS and the simulation is show 1.008s/27.273mS.

It's comical to see the times out to so many decimal places. What's the tolerance of the resistors and capacitor?

If a small number of ms will make a difference, you shouldn't be using a 555 timer.

 

It's comical to see the times out to so many decimal places. What's the tolerance of the resistors and capacitor?

If a small number of ms will make a difference, you shouldn't be using a 555 timer.

Those are just the values I calculated. Really, I need the high time to be as close to 1 seconds and the low time to be in the millisecond range, although this isn't as important. Currently I am just prototyping it but when I actually build the final circuit on a PCB I plan on using 1% or less resistors/capacitors to keep the timing as accurate as possible.

I went ahead and build the circuit with the values I already described (30K, 750, and 47uF) and the circuit partially works. It stays high for 1 second, low for about 25ms, however the cycle is not consistent. It will work for about 6-7 cycles, then stay high for about 5 seconds, before returning to the normal cycle. I left it run for a good minute and it consistently did this. I've never seen this with a 555 before and was thinking maybe it had something to do with the high value of the capacitor (i.e., 47uF) but this is me just completely guessing. Any ideas why it would do this every 6-7 cycles (Note: This is the circuit I shared in the original post)?