Traffic Light controller using logic gates and Finite state machine

Thread Starter

chipstriker

Joined Sep 3, 2014
7
Hello.

I am reasonably new to logic circuits and would like some help on my design of the traffic light controller. I have been tasked this project without much prior knowledge and would appreciate help to critique my design.

Some required parts such as the 555 timer and push button circuits have been have been designed and they work.

here is the project requirement:

A traffic light controller produces five output signals.
Three output signals named Veh_Red, Veh_Amber, Veh_Green control the flow of vehicles while the other two signals named Man_Red, Man_Green control the flow of pedestrians. Veh_Red and Man_Green are always asserted at the same time. Similarly, it applied on Veh_Green and Man_Red. Each traffic light indicator will last for seven seconds in the following steps:

1) 7 seconds for Veh_Red and Man_Green
2) 7 seconds for Veh_Green and Man_Red
3) 7 seconds for Veh_Amber

The process is repeated. A push button is used for pedestrians to cross the road. Three seconds after
pressing the push button, the traffic light controller will trigger to the step (3), 7 seconds for
Veh_Amber. So the pedestrians can cross the road after ten seconds pressing the button. A seven
segment display is used to show the remaining time for pedestrians to cross the road. It only works
in Step (1). It is noted that push button should not work during Step (1) and the 3-second waiting
time.

Project Guideline:
: Implement the push button and a three second counter
: Implement the main controller part
: Implement the seven segment display


The main problem i have is that i am not sure of how to ensure that each state lasts for 7 secs and 3 secs .


Heres what i have done so far ( see uploaded pics )

-- created the state diagrams
--output encoding
--current state and next state with input
--simplified using k-maps
 

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Thread Starter

chipstriker

Joined Sep 3, 2014
7
Hello ScottWang Thanks for the reply.
for the counter part, i have made a MOD 3 and MOD 7 counter using 74191.
The 555 timer is also complete.

I am really confused for the controller part.
 

ScottWang

Joined Aug 23, 2012
7,213
Are you trying to set 555 to 1Sec as 1Sec timebase and mod 3 to 3Sec and Mod 7 to 7Sec?
But you still need to executing the three 7 sec cycle, what is the EE parts?
Are you limited only 191 can be to used for this project?
 

Thread Starter

chipstriker

Joined Sep 3, 2014
7
Yes, i have set the 555 timer to 1 sec and hence the MOD 3 counts 3 sec and MOD 7 counts 7sec.

Yes i need to execute the three 7 sec cycles and one 3 sec cycle.

The parts that i have avaliable are
1
Quad 2-input NAND gates
7400
2
Quad 2-input NOR gates
7402
3
Hex inverters
7404
4
Quad 2-input AND gates
7408
5
Dual 4-input NAND gates
7420
6
Dual 4-input AND gates
7421
7
Quad 2-input OR gates
7432
8
Quad 2-input XOR gates
7486
9
Triple 3-input AND gates
7411
10
Dual 4-input NAND gates
7420
11
Dual 4-input AND gates
7421
12
Triple 3-input NOR gates
7427
13
BCD to 7-segment Decoder
7447/7448
14
4 bit magnitude comparator
7485
15
3 to 8 Line decoder / demultiplexer
74138
16
Dual 2 to 4 line decoder / demultiplexer
74139
17
Quad 2 to 1 line data selector/multiplexer
74157
18
Hex D-type flip flop
74174
19
Quad D-type flip flop
74175
20
Synchronous 4-bit up/down counter with mode control
74191
21
Synchronous 4-bit up/down counter with dual clock
74193
4
22
Dual D-type flip flop with preset and clear
7474
23
4 bit universal bi-directional shift register
74194
24
4 bit binary adder
74283

Other parts can be used too if i can find them ...
I have access to 74193 too.
 
Last edited:

ScottWang

Joined Aug 23, 2012
7,213
Now you have to draw your block diagram that it is similar as the real logic circuit transfer from your attached files pg1 and pg2.
 

Thread Starter

chipstriker

Joined Sep 3, 2014
7
The state diagrams that i designed did not take into account the 7 secs and 3 secs count per state.
This is the part that i am sure i did wrong.
 

ScottWang

Joined Aug 23, 2012
7,213
The state diagrams that i designed did not take into account the 7 secs and 3 secs count per state.
This is the part that i am sure i did wrong.
When we designing the software then we will using the flowchart to describe all the procedure of program, if the description of flowchart are all right then when we writing the program will be all right, that's what I want you to do, transferring the state diagrams to logic gates, if anything wrong then back to modify the state diagrams, and doing the things as above repeat again.
 

Thread Starter

chipstriker

Joined Sep 3, 2014
7
Hello again thanks for the reply. Please forgive me for my ignorance...
I am not sure what software to use to describe the procedure of the program.
 

ScottWang

Joined Aug 23, 2012
7,213
Hello again thanks for the reply. Please forgive me for my ignorance...
I am not sure what software to use to describe the procedure of the program.
I'm not asking you to using the software, that just made an example, but if you want to writing the program then using Arduino Nano or Arduino Micro is a good choice.

search on the right top for "Arduino Nano" and "Arduino Micro".
http://arduino.cc
 

Thread Starter

chipstriker

Joined Sep 3, 2014
7
Sadly, this project does not allow me to use any programmable logic devices.

For implementing the logic from the state diagrams, i have already done it. See pg2 of the Pdf
 
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