Hi! i am tasked to design and create a three input xor logic gate using a mosfet transistor. by the use of LEDs as my input/output indicators, (if the LED lights up, logic value = 1; otherwise, 0). ICs are not allowed.

As i have searched through the net, an xor can be made by "anding the or with a nand" and i was also able to encounter a 2 input xor logic gate which looks like this: My problem is i dont quite get how i will be able to make a functioning circuit which compromises of a three input xor logic gate by using a mosfet.
any suggestions is welcome

 

Hi! i am tasked to design and create a three input xor logic gate using a mosfet transistor. by the use of LEDs as my input/output indicators, (if the LED lights up, logic value = 1; otherwise, 0). ICs are not allowed.

As i have searched through the net, an xor can be made by "anding the or with a nand" and i was also able to encounter a 2 input xor logic gate which looks like this: My problem is i dont quite get how i will be able to make a functioning circuit which compromises of a three input xor logic gate by using a mosfet.
any suggestions is welcome

XOR is an odd logic chip. Looking at it, you end up with a question whether "exclusive" really means exclusive or not. Get a datasheet from a commercially available chip and you'll see it is more of an odd party checker than an exclusive OR chip.

 

my progress so far... with a two input xor logic gate
seems I cant find where and what I've done wrong lol.

 

my progress so far... with a two input xor logic gate
seems I cant find where and what I've done wrong lol.

You seem to have some gaps (shorts) between transistors that need to be finished.

Also, is there supposed to be some sort of output between Q1 and Q8. If not, what is the point of these two transistors?

 

I would define an exclusive OR as any 1 at an input gets through EXCEPT when all inputs are a 1, so I would disagree with GopherT's chart. This gives a 1 output when any one or all three inputs are a 1. And the "inverse", gives a 0 when any two inputs are a 1 or all three are 0s. Try to extend this to four inputs.
So you NAND the inputs and AND the output of the NAND with the OR of the inputs.
Frank

 

I would define an exclusive OR as any 1 at an input gets through EXCEPT when all inputs are a 1, so I would disagree with GopherT's chart. This gives a 1 output when any one or all three inputs are a 1. And the "inverse", gives a 0 when any two inputs are a 1 or all three are 0s. Try to extend this to four inputs.
So you NAND the inputs and AND the output of the NAND with the OR of the inputs.
Frank

This topic has been hashed and re-hashed on this site. It is not a question of whether or not you agree with it, it is a question of what evolved into an industry standard. You can feel free to invent your own "Chucky-XOR" that behaves that way. No other commercially available 3 or more input XOR gate does.

 

I would define an exclusive OR as any 1 at an input gets through EXCEPT when all inputs are a 1, so I would disagree with GopherT's chart. This gives a 1 output when any one or all three inputs are a 1. And the "inverse", gives a 0 when any two inputs are a 1 or all three are 0s. Try to extend this to four inputs.
So you NAND the inputs and AND the output of the NAND with the OR of the inputs.
Frank

The issue of what a multi-input XOR gate "should" be is very debatable. The issue of what a multi-input XOR gate "is" is pretty well-established industry convention -- it is an odd parity checker and is HI whenever an odd number of inputs are HI.

 

update on my circuit~
found a pattern for a 3 input xor gate on this site
but Multisim keeps popping a simulation error. I dont know what to do ._.

 

What is the simulation error? We are not mind readers.

 

my progress so far... with a two input xor logic gate
seems I cant find where and what I've done wrong lol.

Look at P3 of the datasheet attached. You will immediately know where your mistakes are...

Allen

 

What is the simulation error? We are not mind readers.

Sorry i thought i uploaded the report txt
here~

 

Look at P3 of the datasheet attached. You will immediately know where your mistakes are...

Allen

Thanks! you're right. haha it seems I've complicated this circuit more than it should be.

 

Look at P3 of the datasheet attached. You will immediately know where your mistakes are...

Allen

i'm sorry it seems that im a little lost, did my placement for my vdd and vss incorrect?

im sure that I correctly placed the mosffet based on this diagram i found here:

I'm sorry for such a long delay, but the solution to my problem (schematic for 3-input XOR) turned out to be as follows:

Thanks to everyone who helped out.

n

 

You aren't going to learn nearly as much as you think you might by finding someone else's solution and copying it.

The goal of the exercise is for YOU to use the skills and knowledge YOU have attained to solve a problem. You should be able to take an arbitrary truth table and implement it directly in CMOS. What will you do next time when a customer needs a function implemented in silicon and you can't find someone else that happens to have posted a solution for that exact problem?

 

i'm sorry it seems that im a little lost, did my placement for my vdd and vss incorrect?

im sure that I correctly placed the mosffet based on this diagram i found here:

n

I merely want to point out that in the diagram in post #3, the p-mosfet are all drawn backwards. You's have to correct this mistake and make the 2-input XOR gate work first before you have any chance with the 3-input XOR.

The circuit in post#1 is a theoretical one. After adding in the input switches and the NOT_A and NOT_B stage, it won't be that simple any more...

Allen

 

You aren't going to learn nearly as much as you think you might by finding someone else's solution and copying it.

The goal of the exercise is for YOU to use the skills and knowledge YOU have attained to solve a problem. You should be able to take an arbitrary truth table and implement it directly in CMOS. What will you do next time when a customer needs a function implemented in silicon and you can't find someone else that happens to have posted a solution for that exact problem?

I'm sorry, just so you know I tried doing what you've said and made my own design but unfortunately it contains many transistors and halfway I stopped working on it after spending huge time and seeing this one which contains less transistor which looks simple made me envious so I've decided to use it.

Well you could say that I just got lazy or whatever. I'm also guilty for what I've done, copying someone else's work and for that I'm terribly sorry. I'm not gonna do that again, I'm just frustated that the set deadline is just around the corner and I havent done anything that's working so i copied it. aah this is embarassing

 

I merely want to point out that in the diagram in post #3, the p-mosfet are all drawn backwards. You's have to correct this mistake and make the 2-input XOR gate work first before you have any chance with the 3-input XOR.

The circuit in post#1 is a theoretical one. After adding in the input switches and the NOT_A and NOT_B stage, it won't be that simple any more...

Allen

ohh so you were referring to the first circuit!
Yeah you're right. my bad haha
i'll try working on it
thanks~

 

I've decided to replace my my previous 2input xor circuit by this circuit
As one can see, I've used an OR and NAND gate in input A and B and then ANDED the output. But then again,there's a simulation error that popped up namely, the numeric overflow in device model. Any thoughts how to resolve this error?

 

I'm sorry, just so you know I tried doing what you've said and made my own design but unfortunately it contains many transistors and halfway I stopped working on it after spending huge time and seeing this one which contains less transistor which looks simple made me envious so I've decided to use it.

Well you could say that I just got lazy or whatever. I'm also guilty for what I've done, copying someone else's work and for that I'm terribly sorry. I'm not gonna do that again, I'm just frustated that the set deadline is just around the corner and I havent done anything that's working so i copied it. aah this is embarassing

So let's see if we can get you where you are supposed to be in order to design this circuit yourself.

In a pure CMOS logic circuit, the term "Complementary MOS" is more than just a marketing name -- it is the design philosophy for implementing logic circuits. You have a certain logic function implemented using NFETs to pull the output down and the complement of that same logic implemented in PFETs to pull the output up. So you can focus on one and then take the complement to get the other.

An OR function is created by putting FETs in parallel and an AND function is created by putting them in series. So let's look at the following function

Y = AB + A'B'

This can be thought of as

Y = W + X

where W and X are two functions of A and B.

This means that I want the output to be HI when either W is true OR when X is true, which means that the realization of W and X are in parallel in the pullup portion of the circuit. It also means that, in the pulldown portion, the complements, W' and X', are in series.


Now we can focus on implementing W and X and their complements

W = AB

which means that we want to implement FETs in series, one that pulls up when A is HI and the other that pulls up when B is HI.

W = A'B'

also means that we want to implement FETs in series, but with one that pulls up with A is LO and the other that pulls up when B is LO.

Because of the inverting nature of FETs, to get a PFET to pullup when A is HI, we need to apply A' to its gate. With this in mind, we have, for the pullup section:

Now you see if you can design the pulldown section using NFETs.

 

I've decided to replace my my previous 2input xor circuit by this circuit
As one can see, I've used an OR and NAND gate in input A and B and then ANDED the output. But then again,there's a simulation error that popped up namely, the numeric overflow in device model. Any thoughts how to resolve this error?View attachment 98940

Yes that might work. Too bad Q11, Q12, Q15, Q16 is a NOR gate.

It is very hard to read your circuit. Can you make the connection dots larger?
Why Q10 gate is grounded?

Allen