Temperature compensation in MOSFET on resistance measurement with thermistor

Thread Starter

Engineering_Junkie

Joined Sep 9, 2015
41
Hey everyone,

I'm a little stumped by this. I'm using an infineon ir25750l to measure the voltage drop across a MOSFET and this application note: http://www.infineon.com/dgdl/an-1199.pdf?fileId=5546d462533600a40153559b2426115e


On page 9 they show a circuit used to compensate for variations in temperature but I have no idea how this accounts for variation. If the CS pin is at 0.21 volts then in my opinion that voltage is fixed at that and can't be raised or lowered with this circuit?

Thanks in advance for any help.
 

AlbertHall

Joined Jun 4, 2014
10,057
There is resistance within the chip between VS and CS. The temperature compensation adds resistance to COM from the CS pin which will load the CS pin and reduce the voltage there. This loading varies with temperature and the values are calculated to match MOSFET or IGBT temperature coefficient.
 

Thread Starter

Engineering_Junkie

Joined Sep 9, 2015
41
Thanks for the reply! definitely understand it slightly better. I can see the resistors and mosfet form a divider from the VS pin to CS like this: http://imgur.com/a/sn1TT

I also now understand that the the thermistor and resistors add extra loading to the CS pin with the 50K ohm in the first picture being varied as it is now in parallel with the temperature compensation circuit.

I don't understand why the 12V is coupled to the temperature compensation circuit though as shown here : http://imgur.com/a/vrawd

thanks in advance for any help
 

Thread Starter

Engineering_Junkie

Joined Sep 9, 2015
41
Thanks Alberthall, i understand that, but it's directly coupled to the temperature compensation circuit, how will it influence the CS pin?

thanks in advance for any help:)
 

Alec_t

Joined Sep 17, 2013
11,414
I'm wondering if Fig 8 in the Appcn Note is in fact correct? It makes no sense to me either to impose (via R1) the (large and uncompensated) PGEN voltage on the small CS voltage that is being sensed and supposedly compensated. I would expect PGEN and the 47R gate resistor to be entirely independent of the compensation network.
 

AlbertHall

Joined Jun 4, 2014
10,057
I'm wondering if Fig 8 in the Appcn Note is in fact correct? It makes no sense to me either to impose (via R1) the (large and uncompensated) PGEN voltage on the small CS voltage that is being sensed and supposedly compensated. I would expect PGEN and the 47R gate resistor to be entirely independent of the compensation network.
Yes, I thought the same, but I could find no diagram that shows that and no comments that it was wrong.
 

Thread Starter

Engineering_Junkie

Joined Sep 9, 2015
41
That's exactly whats been so confusing for me, i contacted infineon to ask for some clarification and just received a message that I should use the values as is, I've requested further clarification though. I'm thinking of using a voltage divider on the CS pin with a thermistor to just adjust the value of the divided voltage output with temperature.
 

Jony130

Joined Feb 17, 2009
5,176

Thread Starter

Engineering_Junkie

Joined Sep 9, 2015
41
I'm wondering if Fig 8 in the Appcn Note is in fact correct? It makes no sense to me either to impose (via R1) the (large and uncompensated) PGEN voltage on the small CS voltage that is being sensed and supposedly compensated. I would expect PGEN and the 47R gate resistor to be entirely independent of the compensation network.
What I find weird as well is that on the next page they show the temperature compensated circuit and it fluctuates around 1.4 Volt, that's not a lot concerning the uncompensated was pretty much the same except it varied more, it's not like the gate voltage ramps up the CS pin to a insanely high voltage or anything like that
 

Thread Starter

Engineering_Junkie

Joined Sep 9, 2015
41

Alec_t

Joined Sep 17, 2013
11,414
how did you calculate the values of those?
Trial/error/compromise! Where simulation comes into its own. On the one hand, to reduce output as temperature increases the NTC thermistor should be in the 'bottom half' of a potential divider. On the other hand, if the 'top half' of the divider has too high a value then the output will be drastically attenuated at all temperatures. The optimum values will depend on the particular FET.
 

Thread Starter

Engineering_Junkie

Joined Sep 9, 2015
41
Trial/error/compromise! Where simulation comes into its own. On the one hand, to reduce output as temperature increases the NTC thermistor should be in the 'bottom half' of a potential divider. On the other hand, if the 'top half' of the divider has too high a value then the output will be drastically attenuated at all temperatures. The optimum values will depend on the particular FET.
Finally got a perfect output, thanks for all the help!
 
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