this is the 2 digit bcd up counter testbench code.could anyone correct it for me since in case there is any error .attach with the assignment question
module tb_two_digits_bcd_counter
#(parameter REPEAT_TIME = 100)
();
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Ouput declartion
wire [7:0] tb_w_op_counter;
wire tb_w_op_synch_tablet;
wire tb_w_op_synch_bottle;
//Input declartion
reg tb_r_ip_count_restart;
reg tb_r_ip_tablet_in;
reg tb_r_ip_bottle_in;
//Wire and register require
reg tb_r_clk;
reg tb_r_sys_reset;
integer delay=25;
wire tb_w_op_edge_tablet;
//***********************************************************************
//Module instantation
//***********************************************************************
counter
test_counter
(.op_counter(tb_w_op_counter),
.ip_tablet_in(tb_w_op_edge_tablet),
.ip_bottle_in(tb_w_op_synch_bottle),
.ip_count_restart(tb_r_ip_count_restart),
.clock(tb_r_clk),
.sys_reset(tb_r_sys_reset));
edge_detector_counter
ip_edge
(.op_edge(tb_w_op_edge_tablet),
.ip_edge(tb_w_op_synch_tablet),
.clock(tb_r_clk),
.sys_reset(tb_r_sys_reset));
synchronizer_bcd
synch
(.op_synch_tablet(tb_w_op_synch_tablet),
.op_synch_bottle(tb_w_op_synch_bottle),
.ip_asynch_tablet(tb_r_ip_tablet_in),
.ip_asynch_bottle(tb_r_ip_bottle_in),
.sys_clock(tb_r_clk),
.sys_reset(tb_r_sys_reset));
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Clock generation
initial tb_r_clk = 1'b0;
always #5 tb_r_clk = ~tb_r_clk;
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Signals intialization
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Sim time=0
initial begin
tb_r_sys_reset = 1'b1;
tb_r_ip_bottle_in = 1'b0;
tb_r_ip_tablet_in = 1'b0;
tb_r_ip_count_restart = 1'b0;
#10 tb_r_sys_reset = 1'b0;
#20 tb_r_ip_bottle_in = 1'b1;
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Test case: Bottle_in
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@(posedge tb_r_clk)
t_test_bottle_in(1,0); //Bottle detect no reset
@(posedge tb_r_clk)
t_test_bottle_in(1,0); //Bottle detect no reset
@(posedge tb_r_clk)
t_test_bottle_in(1,1); //Bottle detect ,count reset
@(posedge tb_r_clk)
t_test_bottle_in(0,1); //Bottle no detect ,count reset
repeat(10) @(posedge tb_r_clk)
$stop;
end
//***********************************************************************
//Task repeat signal pattern
//***********************************************************************
//Task: test bottle in
task t_test_bottle_in
(input reg tip_bottle,
input reg tip_count_restart);
begin
repeat(REPEAT_TIME) begin@(posedge tb_r_clk)
tb_r_ip_bottle_in = tip_bottle;
#100 tb_r_ip_count_restart = tip_count_restart;
repeat(3) begin @(posedge tb_r_clk)
tb_r_ip_tablet_in = 1'b1;
delay = delay +5;
#delay tb_r_ip_tablet_in = 1'b0;
end
delay = 25;
end
end
endtask
//************************************************************************
endmodule
module tb_two_digits_bcd_counter
#(parameter REPEAT_TIME = 100)
();
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Ouput declartion
wire [7:0] tb_w_op_counter;
wire tb_w_op_synch_tablet;
wire tb_w_op_synch_bottle;
//Input declartion
reg tb_r_ip_count_restart;
reg tb_r_ip_tablet_in;
reg tb_r_ip_bottle_in;
//Wire and register require
reg tb_r_clk;
reg tb_r_sys_reset;
integer delay=25;
wire tb_w_op_edge_tablet;
//***********************************************************************
//Module instantation
//***********************************************************************
counter
test_counter
(.op_counter(tb_w_op_counter),
.ip_tablet_in(tb_w_op_edge_tablet),
.ip_bottle_in(tb_w_op_synch_bottle),
.ip_count_restart(tb_r_ip_count_restart),
.clock(tb_r_clk),
.sys_reset(tb_r_sys_reset));
edge_detector_counter
ip_edge
(.op_edge(tb_w_op_edge_tablet),
.ip_edge(tb_w_op_synch_tablet),
.clock(tb_r_clk),
.sys_reset(tb_r_sys_reset));
synchronizer_bcd
synch
(.op_synch_tablet(tb_w_op_synch_tablet),
.op_synch_bottle(tb_w_op_synch_bottle),
.ip_asynch_tablet(tb_r_ip_tablet_in),
.ip_asynch_bottle(tb_r_ip_bottle_in),
.sys_clock(tb_r_clk),
.sys_reset(tb_r_sys_reset));
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Clock generation
initial tb_r_clk = 1'b0;
always #5 tb_r_clk = ~tb_r_clk;
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Signals intialization
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Sim time=0
initial begin
tb_r_sys_reset = 1'b1;
tb_r_ip_bottle_in = 1'b0;
tb_r_ip_tablet_in = 1'b0;
tb_r_ip_count_restart = 1'b0;
#10 tb_r_sys_reset = 1'b0;
#20 tb_r_ip_bottle_in = 1'b1;
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Test case: Bottle_in
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@(posedge tb_r_clk)
t_test_bottle_in(1,0); //Bottle detect no reset
@(posedge tb_r_clk)
t_test_bottle_in(1,0); //Bottle detect no reset
@(posedge tb_r_clk)
t_test_bottle_in(1,1); //Bottle detect ,count reset
@(posedge tb_r_clk)
t_test_bottle_in(0,1); //Bottle no detect ,count reset
repeat(10) @(posedge tb_r_clk)
$stop;
end
//***********************************************************************
//Task repeat signal pattern
//***********************************************************************
//Task: test bottle in
task t_test_bottle_in
(input reg tip_bottle,
input reg tip_count_restart);
begin
repeat(REPEAT_TIME) begin@(posedge tb_r_clk)
tb_r_ip_bottle_in = tip_bottle;
#100 tb_r_ip_count_restart = tip_count_restart;
repeat(3) begin @(posedge tb_r_clk)
tb_r_ip_tablet_in = 1'b1;
delay = delay +5;
#delay tb_r_ip_tablet_in = 1'b0;
end
delay = 25;
end
end
endtask
//************************************************************************
endmodule
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