Stuck at fault & Memories testing

loosewire

Joined Apr 25, 2008
1,686
You are answering questions with thousands of experts looking this over ,you must

that a lot of experts don't believe in doing home work students. I have to give credit

for taking the time to learn more about yourself. I do presentations in front of large

groups of professional people ,most could not answer your question. Your type of

question has a few pay for answers web sites. Keep trying to post your working

materials and diagrams ,if you get it right some one will agree with you .I did find

Indian professor on U-tube drawing out diagram ,try some the Indian online sites.
 

loosewire

Joined Apr 25, 2008
1,686
My last post would not go thru ,sorry about that. It was a long one.

I will let it go for now ,keep working on your project.
 

tshuck

Joined Oct 18, 2012
3,534
@tshuck Thank you very much for your reply. Can you please explain this with simple circuit with logic gates.
Take a CMOS AND gate:


What happens if one of the output driving transistors (in the inverter stage) were to fail and the drain and source provided a low impedance path? Now, what happens if, instead, the other fails in this manner? How does this affect the rest of the circuit that this AND gate is attached to? The output will no longer track the inputs.
 
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