I'm exploring DMA on a Nucleo board and seeing unexpected behavior.

As I step through code I can see that various writes have no effect, i.e.:

    DMA2->HIFCR = 0x00000F40;   
    DMA2_Stream5->PAR = (uint32_t)&(DAC->DHR12R1);
    DMA2_Stream5->M0AR = (uint32_t)&(SINEWAVE);
    DMA2_Stream5->NDTR = 4096;
    DMA2_Stream5->CR  = 0x0E000000; // Channel 7
    DMA2_Stream5->CR |= 0x00005440;
    DMA2_Stream5->CR |= 0x00000016;
    DMA2_Stream5->FCR = 0;

After each statement the target registers are all 0 !!

All other registers that I write to, do modify the registers - like RCC, GPIOA (MODER) etc - all of these get changed as expected as I step through the code.

This seems like something very fundamental - but what?

 

OK it seems that failing to enable the clock for DMA2 was the issue, these register writes now do cause updates!!

 

OK this is still puzzling, yes I can now see changes get made to the various DMA2_Stream registers but HIFCR remains at zero, writing to it seems to have no effect...

I asked the question in more detail at the ST website here.

 

It is often the case with I/O registers, that you cannot read back what you wrote. That is they are write-only registers. In many cases, what you read back may be null or a completely different set of bits. What you should do is look for causal effects. If I write x to Registe 1, I should be able to observe y by reading Register n. I know that digging this information out can be tedious, but there really is no other way. Good Luck

 

It might be a "write to clear" status register. It might be full of interrupt flags which are set by the DMA controller and cleared by writing a "1" to the bit. Writing a 1 to a bit does not set the bit to a "1", only resets it to "0". Actually, writing a "1" to this register clears a bit in another register. In this regard, the register is "write only". The reference manual will say which flag in another register is reset by this register. Other DMA controllers combine the status flag and the "write to clear" function in one register. STM32 seems to use two registers.

 

From the reference manual. Bold emphasis is mine:

"Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register"