Hello All, First time poster so be gentle!
I wish to make a real-time SPDIF stereo splitter that takes a standard SPDIF input and has two outputs; left and right channel audio respectively. Please see a pictorial representation below:

I wish the device to have as little latency as possible therefore it makes sense to keep the components to a minimum. I have reasonable experience in embedded microcontrollers and a tiny bit of experience with FPGAs; the FPGA route must be the lowest latency method of doing this but my inexperience with the SPDIF protocol limits me from implementing the proposed. I understand some microcontrollers have SPDIF ports but usually 1 - I need three. One option I have toyed with is to convert the SPDIF signal to I2S but again, I am finding it difficult to source a microcontroller that has more than 2 I2S ports and the extra conversion step will add latency. Can anybody with more experience with SPDIF suggest a solution close to optimal but reasonably easy to implement?
I wish to make a real-time SPDIF stereo splitter that takes a standard SPDIF input and has two outputs; left and right channel audio respectively. Please see a pictorial representation below:

I wish the device to have as little latency as possible therefore it makes sense to keep the components to a minimum. I have reasonable experience in embedded microcontrollers and a tiny bit of experience with FPGAs; the FPGA route must be the lowest latency method of doing this but my inexperience with the SPDIF protocol limits me from implementing the proposed. I understand some microcontrollers have SPDIF ports but usually 1 - I need three. One option I have toyed with is to convert the SPDIF signal to I2S but again, I am finding it difficult to source a microcontroller that has more than 2 I2S ports and the extra conversion step will add latency. Can anybody with more experience with SPDIF suggest a solution close to optimal but reasonably easy to implement?