Should The output Z be High or Low in this circuit ?

WBahn

Joined Mar 31, 2012
30,052
What's the point of confusion?

Since Z is the logical AND of three inputs, isn't Z going to be LO unless ALL of the three inputs are HI?

Why do you have it LO before the final clock goes HI?
 

Thread Starter

s971997

Joined Dec 5, 2017
2
What's the point of confusion?

Since Z is the logical AND of three inputs, isn't Z going to be LO unless ALL of the three inputs are HI?

Why do you have it LO before the final clock goes HI?
Because i'm not sure Should do i have to Consider X Hi or LO ,because it the begging it was Low and just before the Clock goes Hi it became HI .Should i consider the last Value (just before the clock goes Hi) or The First value
 

WBahn

Joined Mar 31, 2012
30,052
Notice that no clock signal is going into that AND gate. An AND gate doesn't care what it;s input signals used to be or what they might become some time in the future. It only cares about what they is right now.
 
Top