guys please can u tell me what would the total propagation delay be for a serial adder for adding 4 five bit no.s?

 

Can't easily answer that. What is the logic family and typical gate delays? - plus the clock frequency plays a part. Are the numbers all in a pipeline, or must each be fetched out of memory and placed in the register individually?

 

If this serial adder is made of logic gates then first you need to find out the propagation delay of each gate. This can be found in the manufacturers data for the gate. It will depend on supply voltage and temperature as well.

Then follow the logic signals through the adder until the correct output appears. Because different input combinations may travel through a different number of gates the total time may depend in the input state. Also, you may find there are "race" conditions between different paths so the output might not get its final value immediately.

There is simulation software that can help you with this.

Normally the designer will arrive at a "worst case" figure and ensure that the output is not used until this time has passed. This is what limits clock speed in micro-controllers, for example.

 

lets just say delay due to the flip flops be d1 and that due to the gates d2........does that help??

 

and can u plz suggest me a nice simulation software??

 

There's Cedar Logic Simulator - http://sourceforge.net/projects/cedarlogic/