Does anyone have the circuit diagram of the successive approximation register (SAR) analog-to-digital converter (ADC)? I have made the circuit of a comparator block of it and needed help with all the remaining blocks. I am simulating in ltspice. I wanted to check the complete working of the comparator and then the converter.

 

This sounds like homework? If so you should post in the Homework Help forum. But we don't give answers, only assist with working through problems you've already had ago at. The SAR architecture is well documented, a quick Google will find several examples. The register is usually implemented with a state machine & lookup table rather than combinatorial logic - Circuit Digest has a good explanation of the process