It would indeed appear that they are taking 4 samples and averaging them to make one output bit.I don't know what I am referring to. I take this course online on edx and in the first week they introduce this notion out of thin air. I asked on their forum and I still wait for an answer.
Maybe this other slide would make more sense.
Yes, it is sort of strange but it's the way many serial converters work under the hood. On a PIC with a EUSART the internal receive data recovery block is a 16X shifter that samples 16 times per bit time slot to determine if it's a one or zero. So they are using a 1 bit 'ADC' to oversample the input for 1 bit before it goes to the serial data shift register.It would indeed appear that they are taking 4 samples and averaging them to make one output bit.
As I noted, the only converter type I know of that (sort of) does that is a sigma-delta.
It does seem an odd way to introduce the over-sample concept. I've never seen it represented that way anywhere else.
Normally it's the number of over-samples per output word, not output bit, that's discussed.