Hello all,
I'm trying to think about how to implement a safety feature in my microprocessing system if somehow an interrupt occurs.
My design is currently functional using only polling. However if an interrupt were to somehow occur, my microprocessing system should be able to handle this scenario in a safe and correct manner.
I plan on tieing the IRQ and NMI lines to 5V(they are active low) as a precaution, but as an engineer we must ensure that the design is able to handle the worst case scenarion that an interrupt occurs.
One of the two manners suggested to me for handling this interrupt in a safe manner was to have the microprocessor continually branch to itself if it is interrupted.
Another suggestion was made to that I could have it branch to another device and subesquently recieve have the microprocessor power itself down, powering down the device it branched to as well.
Does anyone else have any other suggestions for a suitable ISR routine? Any suggestions of the design of this routine?
Thanks again!
I'm trying to think about how to implement a safety feature in my microprocessing system if somehow an interrupt occurs.
My design is currently functional using only polling. However if an interrupt were to somehow occur, my microprocessing system should be able to handle this scenario in a safe and correct manner.
I plan on tieing the IRQ and NMI lines to 5V(they are active low) as a precaution, but as an engineer we must ensure that the design is able to handle the worst case scenarion that an interrupt occurs.
One of the two manners suggested to me for handling this interrupt in a safe manner was to have the microprocessor continually branch to itself if it is interrupted.
Another suggestion was made to that I could have it branch to another device and subesquently recieve have the microprocessor power itself down, powering down the device it branched to as well.
Does anyone else have any other suggestions for a suitable ISR routine? Any suggestions of the design of this routine?
Thanks again!