Hello, I know that we should not route signals over split planes, does this apply to LVDS signals as well or only single ended?

 

You want to maintain as much symmetry as possible in order to take advantage of the LVDS.
It also depends on what stage of the system is your signal.
What is the impedance of the driver? If it is very low impedance then it should not matter too much.

 

The driver is an FPGA. As the lines (100Ω controlled impedance) leave the bga pins, some of them cross over a split power plane (20 mils gap) and i'm afraid that this could create problems..

 

You will have to provide a few more details.
What is the receiver and the input impedance?
How long are the traces?
What frequency is the signal?
What is the voltage?
How many loads on the signal?
What other signals are in the vicinity?
Perhaps a circuit diagram might help.

 

Thank you again for your quick reply.. The receiver is another FPGA located in a different board. The two boards are connected with cable (twisted pairs 100Ω, 30 cm length) and the pcb traces is 6 cm long. The connection is point to point and the signal's frequency is 100MHz.

 

Fortunately 100MHz is not too high and your distances of 30cm and 6cm are moderate.
You should not have a problem but I would suggest making sure that the signal pair has as much symmetry as possible and try to maintain the 100Ω impedance as much as possible along the entire signal path.

 

It depends upon the rise and fall times of the signal. If that is less than the 1/2 the propagation delay between the two chips (for the board traces and wire) then you could have reflection problems.

Is there any way to redo the power planes or the signal so that it is routed only over the plane connected to the FPGA driver common?