This will work -- and notice that it employs the constraint that I was talking about. You need to allow enough time for everything to propagate fully before you allow the next thing to happen. In this case, before you can use the counter value, you have to wait that 350 ns or so and that is the fastest that your logic that uses the counter output can run at. Let's call it 3 MHz for simplicity. This is the fastest that your "system clock" can run at. The counter itself can work with a faster input signal because nothing it being done with it's outputs while it is counting, but the counting signal (which, conceptually, isn't a clock but just an input signal to the system) is being gated by the 3 MHz system clock. It disables the input signal to the counter on one clock period and captures the counter's output value on the next.

Now, from an implementation standpoint, cheats and shortcuts can be taken, for instance having a sequencer that enables the gate for one second and, upon expiring, starts a delay that holds off capturing the counter output for the needed propagation time, as long as they observe the constraints where critical. In most systems, those constraints are critical at every clock cycle, placing that upper limit on achievable clock frequency.

Hello again,

So what do you think the maximum input clock signal would be. This would actually be the unknown frequency say at 50 percent duty cycle. The unrelated clock would gate that for 1 second, then latch the counters after 350ns.
For example, for a 20MHz input signal to be measured, the 1 second gate would allow 20 million clock pulses into the first FF of the first counter, then disable the input completely, then after 350ns activate the latches.
The counters are spec'd at 20MHz and let's say that is non variable. Actually it is variable, but I'd be willing to ignore that for now as even 10MHz would be good enough and that would mean just 10 million input clock cycles would be gated into the first FF.

 

What is the part number of the latch?

 

Hello again,

So what do you think the maximum input clock signal would be. This would actually be the unknown frequency say at 50 percent duty cycle. The unrelated clock would gate that for 1 second, then latch the counters after 350ns.
For example, for a 20MHz input signal to be measured, the 1 second gate would allow 20 million clock pulses into the first FF of the first counter, then disable the input completely, then after 350ns activate the latches.
The counters are spec'd at 20MHz and let's say that is non variable. Actually it is variable, but I'd be willing to ignore that for now as even 10MHz would be good enough and that would mean just 10 million input clock cycles would be gated into the first FF.

As long as you didn't exceed the max spec'ed frequency for the counter (the 20 MHz in this case), you should be fine. Having said that, you need to look closely to make sure than things like minimum rise and fall times are observed and some counters have a limit on how slow they can count (though that's probably not the case for your parts).

If the counter didn't have a max frequency spec, but rather other timing specs, then you need to analyze what the maximum frequency would be such that all of those specs are satisfied.

 

Even synchronous counters have max f glitches for carry out.

If a scope probe fixes it then you have faster chips than the original design with a metastable problem. If 30 pF fixes it then add it to pin 10 of the AND or up to 100 pF. No need for R as that is built into the gate RdsOn. That's the simple fix.

 

What is the part number of the latch?

Hi,

Well I'd have to remember, maybe 74LS75 but originally 7475 but it is possible to go to a faster latch too as well as counters faster than the LS series. I would think if a series like LS was used for the counters then the latch would be of the same series.

 

Hi,

Well I'd have to remember, maybe 74LS75 but originally 7475 but it is possible to go to a faster latch too as well as counters faster than the LS series. I would think if a series like LS was used for the counters then the latch would be of the same series.

Be careful about thinking that faster is automatically better. I killed a chip by porting the design from a slower to a faster process without adequately verifying it. We were under extremely tight time pressure to get on the fab run -- and our customer was made aware of the risks that we would have to run in order to get it taped out in time for that run instead of waiting the six months for the next run. After we taped, we continued doing the verification sims and noticed that the faster logic resulted in signals propagating through the logic so fast that setup/hold times were not being satisfied. As feared, the chip didn't work when it came out of fab and we had to respin it. Fortunately, having physical, if not working, chips in hand plus simulations results that predicted the failure behavior actually demonstrated by the chips and a modified design ready to go that was fully verified satisfied their customer that the project should continue.

 

SN7475 or SN74LS75 latches are level sensitive, not edge triggered.
The latch is transparent when the ENABLE input is high. Data is retained on the falling edge of ENABLE.

Hence your ENABLE signal has a pulse width which in effect is your clock delay time. This is longer than any propagation delays in the ripple counter outputs. You don’t need a faster latch. You just need to make the ENABLE pulse wider.

 

Be careful about thinking that faster is automatically better. I killed a chip by porting the design from a slower to a faster process without adequately verifying it. We were under extremely tight time pressure to get on the fab run -- and our customer was made aware of the risks that we would have to run in order to get it taped out in time for that run instead of waiting the six months for the next run. After we taped, we continued doing the verification sims and noticed that the faster logic resulted in signals propagating through the logic so fast that setup/hold times were not being satisfied. As feared, the chip didn't work when it came out of fab and we had to respin it. Fortunately, having physical, if not working, chips in hand plus simulations results that predicted the failure behavior actually demonstrated by the chips and a modified design ready to go that was fully verified satisfied their customer that the project should continue.

Oh that's interesting. I'll have to look at this all over again, it's been quite a few years now.
One huge improvement was going from regular original power hungry 74xx series chips to 74LSxx series chips. That cut the power down significantly and thus heat inside the case we down a lot.

 

SN7475 or SN74LS75 latches are level sensitive, not edge triggered.
The latch is transparent when the ENABLE input is high. Data is retained on the falling edge of ENABLE.

Hence your ENABLE signal has a pulse width which in effect is your clock delay time. This is longer than any propagation delays in the ripple counter outputs. You don’t need a faster latch. You just need to make the ENABLE pulse wider.

Oh yes, that's right, but I do not see how much difference that makes because the timing would be such that the 'enable' input would go low when a would-be clock pulse would go high (or low). Given the same logic family throughout, I don't think there would be much difference. Maybe you see a problem there.
I didn't mean get a faster latch, what I was sort of suggesting was that the entire circuit might be made faster by going to a faster TTL logic family. Before I did that though I would probably just use a pre-scale counter. That might divide by 10 before applying the output of that to the first FF in the counter string. That would be used with higher frequency inputs and switched out for lower stuff like 2MHz or 100kHz, etc.

 

Counters commonly change state on the rising edge of the CLOCK. If the latch ENABLE signal is derived from the CLOCK signal then you are ok. The latch will clock the data on the falling edge of ENABLE which comes halfway in the clock cycle.

Fairchild 74F160 and 74F190 counter ICs can be clocked at max 100 MHz, 125 MHz typical. All you need to do is replace the first decade of the frequency counter circuit. Then the remaining decade counters can be clocked at 1/10 frequency of the input clock. I built a frequency counter doing exactly that.