RF Performance Issues - Board Layout?

Thread Starter

byro3227

Joined Oct 21, 2017
4
Hello everyone,

This is my first post to AAC. Over the past few years I've reference these discussion boards rather frequently and I've found them to be quite informative.

I have been working on a wireless sensing application and have some general design questions concerning board layout and can't seem to find consistent guidelines from the various chip manufacturers. I'm looking for some guidance and recommendations to improve the outcome of my design.

Transmission Line Design Questions:
  • I am calculating 50 Ohm Impedance using AppCAD with 4 layer board stack-up from Osh Park
  • Should transmission line impedance be considered as a micro-strip or a wave-guide?
  • When is one preferred over the other? And for my application, with a very short TX line, should I calculate impedance using a microstrip?
  • Atmel Application Note AT02865 – RF design guidelines recommend treating the transmission line as a microstrip when W/H >= 2 and a gap of 4X the dielectric thickness. The Johannson reference design is a two layer board and uses a coplanar waveguide
  • For best performance should I manufacture some PCB's with varying track widths / spacing and then use a VNA to determine the best dimensions? If so, is the length of trace important?

microstrip.jpg

Waveguide.jpg


Board Layout Questions:
  • Should I include a keep-out region under the antenna launch area under the (u.FL) connector or should I leave solid copper pour? If a keep-out is recommended, should it be applied to all layers?
  • Should I extend the ground plane beyond the U.fl connector, or is the current layout okay in that regard?
  • Should I stitch the grounds of top and bottom layers to the RF Gnd area, or just the Surrounding Ground on the Top Layer and leave the bottom disconnected in this area?
  • Per guidance on Nordic Dev Zone, a left a solid copper pour under the BALUN on all layers. I also left copper pour on all layers under the transmission line.
My current board layout is shown below with the following stackup:
  • Layer 1 = Red (Signals / Gnd)
  • Layer 2 = Green (Solid Gnd)
  • Layer 3 = Orange (Power Planes)
  • Layer 4 = Blue (two signals but mostly Gnd)

Top Layer.jpg

Layer 2 - Ground.jpg

Power_Plane.jpg

Bottom_Layer.jpg

Any help is greatly appreciated!

P.S. I'm just a dumb mechanical guy...
 

Thread Starter

byro3227

Joined Oct 21, 2017
4
Here is the TL; DR version:

Should transmission line impedance be considered as a micro-strip or a wave-guide in a 4 layer stack-up with a thin dielectric?

What is the proper layout for a u.FL connector on a 4 layer board? Is a keep-out region under the antenna launch area necessary? And if so what layers should the keep-out are be applied to?
 

andrewmm

Joined Feb 25, 2011
673
On a PCB, impedance matched wires are either micro strip if on surface, or strip line if internal.
wave guides are basically a tube, not easy to make in a PCB.

re the U.Fl connector,

The quick answer is to look at the manufacturers sites, they will have suggested foot prints / keep outs / routing for any RF connector.
 

Thread Starter

byro3227

Joined Oct 21, 2017
4
Thank you for your response.

I'll proceed with implementing the transmission line as a micro-strip.

The Hirose datasheet shows a keepout area for the first layer and I have implemented this in the design.
1602445778063.png
Where I get confused is the ground layer. A Laird Antenna Design Guideline shows a solid ground plane below the antenna launch area, but in a silicon labs application EN928 there is a keepout area. It's not clear what effect this will have on antenna performance...if any.

Laird Antenna Design Guideline

1602446368125.png


Silicon labs application EN928 there is a keepout area on inner layer 1:
1602446235187.png
 

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sparky 1

Joined Nov 3, 2018
384
Microstrip is usually closer to original simulation. The spacing between ground and signal conductor is not independent of the board's DK dielectric, Zo, energy coupling, parasitics and return path. The balanced distribution that is seen in the final assembly include the irregularities or spacing from signal path and connectors and cables. If the largest cable, the 1.37mm low loss is your choice then look at what happens when you go smaller.
 
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Thread Starter

byro3227

Joined Oct 21, 2017
4
Thanks for the information, but I am not sure I follow your last statement.

I do plan to use a Nano VNA to try to match the antenna to the intended frequency. I will use a 13.4 mil thick microstrip based on the AppCAD calculation. If I find my RF performance is insufficient for my purposes, then I will look into characterization of an actual Osh Park board and identify the best strip dimensions using a VNA.

I did find a post on hackaday where someone tried to characterize the impedance of a coplanar waveguide (6 mil gaps) on a Osh Park 4-layer board: https://hackaday.io/project/162998-the-rise-and-fall-of-pulses/log/168604-osh-park-4-layer-coplanar-waveguide.

Interestingly, a trace width of 13.4 to 13.5 mils was closest to 50 ohms which is what AppCAD calculates for a micro-strip, but perhaps this is purely coincidence. It would have been interesting if the hackaday post had also considered micro-strip lines.
 

andrewmm

Joined Feb 25, 2011
673
Rule 1 of RF,
The rules are guide lines,

Rule 2 of RF,
Every one knows best

Rule 3 of RF,
there are many way to "skin the cat", sorry to my feline friends,
if you stick to one persons / companies method, it will work.
don't mix ideas.

Re the last one,
think if you were designing a car, based upon part ideas,
you took the front from say a Porsche and the back from say a Ferrari ,
both are great cars, but half and half, not good.

Which leaves you none the wiser,

My rule of RF,
follow one set of rules, and what ever you do, it will probably work.
may be not as best as it could, but that's learning.

Unless you use a 3D field solve simulator, then RF compared to "digital" is more of an art.

In summary

Connector, use the pad shapes / keep out / breakout given to you by the connector manufacturer,
this is what they have used to simulate and test the connector, anything else and you are at risk of killing the VSWR

Board tracks,
tracks are not a problem at RF, !1 Yes they are lossy, but microstrip or strip line, give lovely matched impedance , provided the board is made as you specify, and loss can be compensated for. Vias are the killer done wrong. Think stubs on a strip line.
read up on stubs here
https://en.wikipedia.org/wiki/Stub_...pline circuit, a,load or the connector itself.

board manufacturing,
In theory , any size board with any stack up can be manufactured,
In practice, each board manufacturer has in stock "standard" set of material.
The normal way to do a RF matched board, is to ask the board manufacturer.
They all have copies of something called polar stack up tool,

Go for a standard board thickness, say 0.8 or 1.6 mm,
tell the manufacturer how many layers and which ones you want as power and which as matched impedance,
and what impedance tracks you want, ( 50 ohm, 75 Ohm single ended or differential, micro or strip line ) and they will come back and tell you what layer stack and what thickness lines to use.

BTW : I'm assuming as your asking m, that your nit at real high frequency , over 30 GHz,
At these frequencies, things become real weird, such a ENIG, coating becomes an inductor, and standard FR4 becomes very lossy / variable.
 
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