This is more a question of how a Microchip PIC responds to an interrupt flag when program flow is already in the Interrupt Service Routine. I know that when program flow enters the ISR, the global interrupt enable bit is cleared. At the end of the ISR, a RETFIE instruction is used which re-enables global interrupts.

What I'm not sure about is that if another Interrupt Flag bit is set during the period between disabling GIE and re-enabling it, will the program respond to it after the current interrupt is executed or will the 2nd flag be ignored? How do PIC chips handle this type of scenario?

Thank You

 

Well... exactly how depends on the code inside the ISR.

If the flag gets set before it is checked then it is handled inside the same ISR call triggered by another event.

If the flag is set after the check happens the ISR exits after handeling the call, but guess what? There is an ISR flag set so the whole ISR gets called again.

So you get stuck looping into the ISR until all flags get reset.

Same thing happens if you forget to reset a flag. You loop de loop endlessly. ;-)

 

Thanks for verifying that. Better to seek verification than to work off assumption.

 

It also depends on if you are using prioritized interrupts.

For instance, the PIC18F series has both low and high priority interrupts. A low priority interrupt can, itself, be interrupted by a high priority interrupt, yet nothing can interrupt a high priority interrupt (short of a reset condition).

An interrupt will, once there are no higher priority interrupts active, execute the ISR and exit. If another interrupt flag is detected, the PIC with return to the ISR and start all over, which is what happens if you forget to clear a flag.