This is more a question of how a Microchip PIC responds to an interrupt flag when program flow is already in the Interrupt Service Routine. I know that when program flow enters the ISR, the global interrupt enable bit is cleared. At the end of the ISR, a RETFIE instruction is used which re-enables global interrupts.
What I'm not sure about is that if another Interrupt Flag bit is set during the period between disabling GIE and re-enabling it, will the program respond to it after the current interrupt is executed or will the 2nd flag be ignored? How do PIC chips handle this type of scenario?
Thank You
What I'm not sure about is that if another Interrupt Flag bit is set during the period between disabling GIE and re-enabling it, will the program respond to it after the current interrupt is executed or will the 2nd flag be ignored? How do PIC chips handle this type of scenario?
Thank You