Hello All,
I have tried to assemble and run schematics using retriggerable monostable from book Marston, Digital Logic IC (page 193). Everything done correct according to the book, but the project does not work ... unfortunately. Output of the chip (pin 5) is just 1.8 V DC instead of
series of pulses as expected.
I have attached pix of the chip, schematics and voltage at pin 5 relative to GND. Only one half of the dual monostable is used (pins 5, 6, 7, 8, 9, 10, 11, 12) the other half is disabled by tying its CLR terminal high and grounding its A and B terminals.
The pin outputs are:
pin 5 1.8V DC
pin 6 48 mV DC
pin 7 1.34V DC
pin 8 35 mV DC
pin 9 - input square pulses
pin10 5.3V DC
pin11 5.3V DC
pin12 4.2V DC
I have tried to assemble and run schematics using retriggerable monostable from book Marston, Digital Logic IC (page 193). Everything done correct according to the book, but the project does not work ... unfortunately. Output of the chip (pin 5) is just 1.8 V DC instead of
series of pulses as expected.
I have attached pix of the chip, schematics and voltage at pin 5 relative to GND. Only one half of the dual monostable is used (pins 5, 6, 7, 8, 9, 10, 11, 12) the other half is disabled by tying its CLR terminal high and grounding its A and B terminals.
The pin outputs are:
pin 5 1.8V DC
pin 6 48 mV DC
pin 7 1.34V DC
pin 8 35 mV DC
pin 9 - input square pulses
pin10 5.3V DC
pin11 5.3V DC
pin12 4.2V DC
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