Hello, I have this great spice model of UCC5304 shown in the datasheet link below and attached as UCC5304_Test.zip
I need to use UCC5304 to open my IRL3915 mosfet as shown in the simple
my R6 are equivalent two connected in parralel CGHV1A250F transistors equivalent it needs 45V and 15A according figure 17.
So when both CGHV1A250F transistors are open its 3||3=1.5ohm.

But I was told not to use the UCC5304 VSS like i do in the last photo because Vss needs to be GND.
But if I PUT gnd on the VSS then my R6 will be ground from both sides.
how to solve this LTspice riddle, how can i simulate this floating voltage from UCC5304?
Thansk.

https://www.ti.com/lit/ds/symlink/u...ivers%2Fisolated-gate-drivers%2Fproducts.html

https://www.alldatasheet.com/datasheet-pdf/pdf/1673867/WOLFSPEED/CGHV1A250F.html

 

Use a large resistance (i.e. 100meg ohm) from the floating circuit common to ground.
Make no other connections (including its power supply from the floating part to ground.
You can use the COM symbol (below) for the isolated common:
That should keep LTspice happy.

 

But I was told not to use the UCC5304 VSS like i do in the last photo because Vss needs to be GND.
But if I PUT gnd on the VSS then my R6 will be ground from both sides.
how to solve this LTspice riddle, how can i simulate this floating voltage from UCC5304?
Thansk.

Look at figure 22 on the TI UCC5304 datasheet.

 

I have done this many times in real life. (not SPICE)

 

Hi yef,
This plot shows the Source/sink currents from Vout, exactly what are you trying to do with this device?
E

 

Hello,I am trying to open and close the mosfter as shown below.
I have connected the circuit as shown below ,However Vgs signal which is going into the mosfet is not toggling by the circuit.It stays the same .maybe the driving bias Vdd and Vssi needs to be a pulse as shown in the datasheet?
Why my Output,loadv is not toggling in the same rate of the input pulse?
LTSPICE file are attached.
Thanks.

 

hi yef,
Try this option.
E

 

Hello Eric,The attached circuit only has capactior between Vdd and VSS.
When I simulated by putting 10K resistor as shown below i dont get the desired signal that you showed.
I simulated exactly the same circuit , why i get a different result?
Thanks.

 

hi yef,
Have you run the asc file I posted,?
E

 

Hello, Its not floating Vgs, I need it to work like ronsimpson said in post 4.
Crutschow suggesting to use 100MEG on the GND
and
" Make no other connections (including its power supply from the floating part to ground. "
Its still not working.Where did I implemented wringly Crutschow words?

ronsimpson said that its real life its a working idia (post 4 schematics),how to make it work in LTspice?
Thanks.

 

Hi,
Note the current level in the Drain, Gate compared to the Source, using your circuit.
E

 

Hello Eric, this is not my connection, I am trying to follow the ronsimpson suggestion.but Apperantly LTspice cannot do it.
Crutschow suggested and advice to overcome this problem but its not working.
Where did i implemented wrong the Crutschow advice?
Thanks.

 

Where did i implemented wrong the Crutschow advice?

How can I tell if you don't show what you did?

Below is an example circuit using an opto isolator:
The output common is isolated from system ground by the 100 megohm resistor, R3.

 

Hello crutschow, I have added a 100Meg as shown below.
What else i need to change in the circuit below?
Thanks.

 

Hello crutschow, I have added a 100Meg as shown below.

That will not work.

Change R1. R1 needs to go from VOUT to VSS or M1-Gate to M1-Source. (VSS is a "ground node" for U1 and M1) It is not the same as ground for VGND.) I don't know if this will help but the real part will not like OUTL being pulled to ground that is VGND.

 

I have added a 100Meg as shown below.
What else i need to change in the circuit below?

That's not correct.
Below is what I meant:
Note that the output common is isolated from the input ground by the 100megohm resistor (for the purposes of the simulation).

 

Hello , my load is not a capacitor .
It’s a mosfet and a resistive load.
Could you draw how to connect my type of load in the method you propose ?
The ground isolation is a tricky thing

 

In SPICE there cannot be floating nodes. Everything must somehow connect to ground.
I circled in green ground. The grounds on the right side are not connected to ground on the left side. (I connected them together by a 100k resistor, value not important.)
In spice when you measure a voltage it is always referenced to ground. (in green) normally you just click on a node. That works for the left side of this schematic.
To measure on the right side, you must measure from (red_ground) to node. Move the mouse to (red_ground) push down on the mouse, move the mouse to M1 Source then release the mouse button. You will get a voltage with a formula like V(N1,N2) which is Node1-Node2.

 

Hello,I have tried to implement this idia as shown bellow.
I have put 100Meg ohm resistor as shown below ,However ltspice creates some error ash snhpwn below.
Where did i go wrong?
Thanks.

 

hi yef,
Try this, 0.1pF added.
E

@yef smith
Add this text to your asc file and remove the 0.1pF