Porting of AT89C2051 micro

Thread Starter

roxi60

Joined Sep 2, 2018
46
Hello.

For PIC micro it’s clear to me that to configure port TRIS register is used and to set pins of the port PORT register is used.

For AT89C20151, it is not clear me, since for instance, when I put P3.4=0, am I configuring pin 4 of port 3 as an output pin or am I setting pin 4 of port 3 to low level?

Thank you
 

MrChips

Joined Oct 2, 2009
19,725
What does the datasheet say?

AT89C2051 ports are open drain with internal pull-ups (with some exceptions).

Correct: Writing to the port, for example P3.4 = 0, will set the pin to the assigned logic level.
To use the port pin as an input, set P3.4 = 1 in order to disable the output transistor.
 

Thread Starter

roxi60

Joined Sep 2, 2018
46
Ok, thank you very much MrChips.
But if I write in the code P3.4=1, how does the software know that I'm configuring an input or I'm setting to an output port the logic level 1?

Thanks again.
 

MrChips

Joined Oct 2, 2009
19,725
When the code sets P3.4 = 1 the active pull-down is disabled. The pin goes to logic 1 because the pin is pulled high through a weak internal pull-up resistor.

An external switch or logic gate is able to pull the pin low and hence present a logic 0 input condition. This is called a wired-OR gate for negative logic, in other words, either 0 condition wins.
 

Papabravo

Joined Feb 24, 2006
12,684
In this part, like many members of the 8051 family, the ports are quasi bi-directional. A '0' written to the port data register enables a "hard" active pulldown that will sink several milliamps. When a '1' is written to the port data register it enables a weak active pullup, typically about 4KΩ. The pullup can only source a few hundred microamps. The weak pullup can be driven low by an external input without causing any damage. Port 0 is usually configured as open drain. You can't get a '1' out of a port 0 pin unless you have an external passive pullup resistor. This was how Intel avoided the need for a DDR (Data Direction Register) in a real estate scarce chip design that first hit the market in 1978
 
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