Hello,In pipeline ADC we have an issue of planning the regions of the flash as shown bellow so in many stages connected we wil not get saturation.
Is there some Video lectrures where they explain how they design pipeline ADC areas shown bellow?
i could not find the logic of making the areas bellow for 1.5 bit 2.5 bit etc..
Thanks.

Is there some Video lectrures where they explain how they design pipeline ADC areas shown bellow?
i could not find the logic of making the areas bellow for 1.5 bit 2.5 bit etc..
Thanks.
