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Yes, a 4K7 resistor. I'm sorry, I forgot it in the schematic.
PIC18F25K22 & 2 x 20 LCD
- Thread starter nerdegutta
- Start date
Are you using the latest Hi-Tech for the 18F chips My old one didn't work I had to update to 9.80 and I'm using MPLAB 8.83 there a bunch of changes from 8.63
I looked at your first post you have the right Hi-Tech just don't no about the MPLAB having a look now
Could you zip your project and post it so I can see if it's compiled the same
I looked at your first post you have the right Hi-Tech just don't no about the MPLAB having a look now
Could you zip your project and post it so I can see if it's compiled the same
I changed from MPLAB on Linux via WINE, to MPLAB 8.83, HI - TECH C for PIC18 MCU (lite) V9.80 on XP, with PICKit3.
Using internal config bits, internal oscillator block and oscillator multi. by 4.
However, there must be something wrong with my breadboarding and powersupply, because I have to check the box "Power target circuit from PICKit3" in the PICKit 3 Settings Power tab.
When I remove the programmer, and connect my powersupply, 5vdc, we're back to the picture in post #21.
I don't know what's happening right now. Need to check power supply wires and the PICKit 3 manual/ICSP connection again.
Thanks for you effort, be80be!
However, there must be something wrong with my breadboarding and powersupply, because I have to check the box "Power target circuit from PICKit3" in the PICKit 3 Settings Power tab.
When I remove the programmer, and connect my powersupply, 5vdc, we're back to the picture in post #21.
I don't know what's happening right now. Need to check power supply wires and the PICKit 3 manual/ICSP connection again.
Thanks for you effort, be80be!
Attachments
Just learned that it is a difference between "debugger" and "programmer" - duh! *face-palm*
I will always need the use of an experienced programmer, MrChips.
I'll keep that in mind, thank you.
Eventually I want the config bits to be in the code.
Yes, I remember opening that file in Firefox, sometimes in the last few days.
Thanks for reminding me.
You can save a lot of time by using the MPLAB assembler include file found in "..\Program Files\Microchip\MPASM Suite" as template. In this case the "P18F25K22.INC" file. By using copy and paste and search and replace you have the config settings done in a few minutes. Here is an example that I think will fit Jens needs. To clean up somewhat. As I think Jens do not need any code protection at all. At this stage. I replaced setting single protection bits. With full register setting (CONFIG5L-CONFIG7H)
Rich (BB code):
// Oscillator Selection bits:
// FOSC = LP LP oscillator
// FOSC = XT XT oscillator
// FOSC = HSHP HS oscillator (high power > 16 MHz)
// FOSC = HSMP HS oscillator (medium power 4-16 MHz)
// FOSC = ECHP EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz)
// FOSC = ECHPIO6 EC oscillator (high power, >16 MHz)
// FOSC = RC External RC oscillator, CLKOUT function on OSC2
// FOSC = RCIO6 External RC oscillator
#pragma config FOSC = INTIO67 //Internal oscillator block
// FOSC = INTIO7 Internal oscillator block, CLKOUT function on OSC2
// FOSC = ECMP EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz)
// FOSC = ECMPIO6 EC oscillator (medium power, 500 kHz-16 MHz)
// FOSC = ECLP EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz)
// FOSC = ECLPIO6 EC oscillator (low power, <500 kHz)
//
// 4X PLL Enable:
// PLLCFG = OFF Oscillator used directly
#pragma config PLLCFG = ON //Oscillator multiplied by 4
//
// Primary clock enable bit:
// PRICLKEN = OFF Primary clock can be disabled by software
// PRICLKEN = ON Primary clock enabled
//
// Fail-Safe Clock Monitor Enable bit:
#pragma config FCMEN = OFF //Fail-Safe Clock Monitor disabled
// FCMEN = ON Fail-Safe Clock Monitor enabled
//
// Internal/External Oscillator Switchover bit:
#pragma config IESO = OFF //Oscillator Switchover mode disabled
// IESO = ON Oscillator Switchover mode enabled
//
// Power-up Timer Enable bit:
#pragma config PWRTEN = ON //Power up timer enabled
// PWRTEN = OFF Power up timer disabled
//
// Brown-out Reset Enable bits:
#pragma config BOREN = OFF //Brown-out Reset disabled in hardware and software
// BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
// BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
// BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
//
// Brown Out Reset Voltage bits:
// BORV = 285 VBOR set to 2.85 V nominal
// BORV = 250 VBOR set to 2.50 V nominal
// BORV = 220 VBOR set to 2.20 V nominal
// BORV = 190 VBOR set to 1.90 V nominal
//
// Watchdog Timer Enable bits:
#pragma config WDTEN = OFF //Watch dog timer is always disabled. SWDTEN has no effect.
// WDTEN = NOSLP WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect
// WDTEN = SWON WDT is controlled by SWDTEN bit of the WDTCON register
// WDTEN = ON WDT is always enabled. SWDTEN bit has no effect
//
// Watchdog Timer Postscale Select bits:
// WDTPS = 1 1:1
// WDTPS = 2 1:2
// WDTPS = 4 1:4
// WDTPS = 8 1:8
// WDTPS = 16 1:16
// WDTPS = 32 1:32
// WDTPS = 64 1:64
// WDTPS = 128 1:128
// WDTPS = 256 1:256
// WDTPS = 512 1:512
// WDTPS = 1024 1:1024
// WDTPS = 2048 1:2048
// WDTPS = 4096 1:4096
// WDTPS = 8192 1:8192
// WDTPS = 16384 1:16384
// WDTPS = 32768 1:32768
//
// CCP2 MUX bit:
#pragma config CCP2MX = PORTB3 //CCP2 input/output is multiplexed with RB3
// CCP2MX = PORTC1 CCP2 input/output is multiplexed with RC1
//
// PORTB A/D Enable bit:
#pragma config PBADEN = OFF //PORTB<5:0> pins are configured as digital I/O on Reset
// PBADEN = ON PORTB<5:0> pins are configured as analog input channels on Reset
//
// P3A/CCP3 Mux bit:
#pragma config CCP3MX = PORTC6 //P3A/CCP3 input/output is mulitplexed with RC6
// CCP3MX = PORTB5 P3A/CCP3 input/output is multiplexed with RB5
//
// HFINTOSC Fast Start-up:
// HFOFST = OFF HFINTOSC output and ready status are delayed by the oscillator stable status
#pragma config HFOFST = ON //HFINTOSC output and ready status are not delayed by the oscillator stable status
//
// Timer3 Clock input mux bit:
#pragma config T3CMX = PORTB5 //T3CKI is on RB5
// T3CMX = PORTC0 T3CKI is on RC0
//
// ECCP2 B output mux bit:
#pragma config P2BMX = PORTC0 //P2B is on RC0
// P2BMX = PORTB5 P2B is on RB5
//
// MCLR Pin Enable bit:
// MCLRE = INTMCLR RE3 input pin enabled// MCLR disabled
#pragma config MCLRE = EXTMCLR //MCLR pin enabled, RE3 input pin disabled
//
// Stack Full/Underflow Reset Enable bit:
#pragma config STVREN = OFF //Stack full/underflow will not cause Reset
// STVREN = ON Stack full/underflow will cause Reset
//
// Single-Supply ICSP Enable bit:
#pragma config LVP = OFF //Single-Supply ICSP disabled
// LVP = ON Single-Supply ICSP enabled if MCLRE is also 1
//
// Extended Instruction Set Enable bit:
// XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
#pragma config XINST = ON //Instruction set extension and Indexed Addressing mode enabled
//
// Background Debug:
// DEBUG = ON Enabled
#pragma config DEBUG = OFF //Disabled
//All code protection turned off
#pragma config CONFIG5L = 0xff
#pragma config CONFIG5H = 0xff
#pragma config CONFIG6L = 0xff
#pragma config CONFIG6H = 0xff
#pragma config CONFIG7L = 0xff
#pragma config CONFIG7H = 0xffThat's a good one.
I'll try that approach.
Thanks!
I'll try that approach.
Thanks!
I take it that most have not seen this file if used you will not have compile errors
Rich (BB code):
#pragma config Settings
Register: CONFIG1H @ 0x300001
IESO = Internal/External Oscillator Switchover bit
OFF Oscillator Switchover mode disabled
ON Oscillator Switchover mode enabled
FOSC = Oscillator Selection bits
RCIO6 External RC oscillator
RC External RC oscillator, CLKOUT function on OSC2
ECMPIO6 EC oscillator (medium power, 500 kHz-16 MHz)
ECMP EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz)
INTIO7 Internal oscillator block, CLKOUT function on OSC2
ECHPIO6 EC oscillator (high power, >16 MHz)
ECHP EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz)
HSMP HS oscillator (medium power 4-16 MHz)
XT XT oscillator
LP LP oscillator
HSHP HS oscillator (high power > 16 MHz)
ECLPIO6 EC oscillator (low power, <500 kHz)
ECLP EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz)
INTIO67 Internal oscillator block
PRICLKEN = Primary clock enable bit
OFF Primary clock can be disabled by software
ON Primary clock enabled
FCMEN = Fail-Safe Clock Monitor Enable bit
OFF Fail-Safe Clock Monitor disabled
ON Fail-Safe Clock Monitor enabled
PLLCFG = 4X PLL Enable
OFF Oscillator used directly
ON Oscillator multiplied by 4
Register: CONFIG2L @ 0x300002
BOREN = Brown-out Reset Enable bits
NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
OFF Brown-out Reset disabled in hardware and software
ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
BORV = Brown Out Reset Voltage bits
250 VBOR set to 2.50 V nominal
190 VBOR set to 1.90 V nominal
285 VBOR set to 2.85 V nominal
220 VBOR set to 2.20 V nominal
PWRTEN = Power-up Timer Enable bit
OFF Power up timer disabled
ON Power up timer enabled
Register: CONFIG2H @ 0x300003
WDTPS = Watchdog Timer Postscale Select bits
8 1:8
1 1:1
32768 1:32768
1024 1:1024
2 1:2
32 1:32
16 1:16
16384 1:16384
128 1:128
4096 1:4096
64 1:64
8192 1:8192
2048 1:2048
512 1:512
256 1:256
4 1:4
WDTEN = Watchdog Timer Enable bits
NOSLP WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect
OFF Watch dog timer is always disabled. SWDTEN has no effect.
ON WDT is always enabled. SWDTEN bit has no effect
SWON WDT is controlled by SWDTEN bit of the WDTCON register
Register: CONFIG3H @ 0x300005
P2BMX = ECCP2 B output mux bit
PORTC0 P2B is on RC0
PORTB5 P2B is on RB5
CCP2MX = CCP2 MUX bit
PORTC1 CCP2 input/output is multiplexed with RC1
PORTB3 CCP2 input/output is multiplexed with RB3
PBADEN = PORTB A/D Enable bit
OFF PORTB<5:0> pins are configured as digital I/O on Reset
ON PORTB<5:0> pins are configured as analog input channels on Reset
CCP3MX = P3A/CCP3 Mux bit
PORTC6 P3A/CCP3 input/output is mulitplexed with RC6
PORTB5 P3A/CCP3 input/output is multiplexed with RB5
MCLRE = MCLR Pin Enable bit
INTMCLR RE3 input pin enabled; MCLR disabled
EXTMCLR MCLR pin enabled, RE3 input pin disabled
HFOFST = HFINTOSC Fast Start-up
OFF HFINTOSC output and ready status are delayed by the oscillator stable status
ON HFINTOSC output and ready status are not delayed by the oscillator stable status
T3CMX = Timer3 Clock input mux bit
PORTC0 T3CKI is on RC0
PORTB5 T3CKI is on RB5
Register: CONFIG4L @ 0x300006
DEBUG = Background Debug
OFF Disabled
ON Enabled
STVREN = Stack Full/Underflow Reset Enable bit
OFF Stack full/underflow will not cause Reset
ON Stack full/underflow will cause Reset
XINST = Extended Instruction Set Enable bit
OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
ON Instruction set extension and Indexed Addressing mode enabled
LVP = Single-Supply ICSP Enable bit
OFF Single-Supply ICSP disabled
ON Single-Supply ICSP enabled if MCLRE is also 1
Register: CONFIG5L @ 0x300008
CP0 = Code Protection Block 0
OFF Block 0 (000800-001FFFh) not code-protected
ON Block 0 (000800-001FFFh) code-protected
CP1 = Code Protection Block 1
OFF Block 1 (002000-003FFFh) not code-protected
ON Block 1 (002000-003FFFh) code-protected
CP2 = Code Protection Block 2
OFF Block 2 (004000-005FFFh) not code-protected
ON Block 2 (004000-005FFFh) code-protected
CP3 = Code Protection Block 3
OFF Block 3 (006000-007FFFh) not code-protected
ON Block 3 (006000-007FFFh) code-protected
Register: CONFIG5H @ 0x300009
CPD = Data EEPROM Code Protection bit
OFF Data EEPROM not code-protected
ON Data EEPROM code-protected
CPB = Boot Block Code Protection bit
OFF Boot block (000000-0007FFh) not code-protected
ON Boot block (000000-0007FFh) code-protected
Register: CONFIG6L @ 0x30000A
WRT0 = Write Protection Block 0
OFF Block 0 (000800-001FFFh) not write-protected
ON Block 0 (000800-001FFFh) write-protected
WRT1 = Write Protection Block 1
OFF Block 1 (002000-003FFFh) not write-protected
ON Block 1 (002000-003FFFh) write-protected
WRT2 = Write Protection Block 2
OFF Block 2 (004000-005FFFh) not write-protected
ON Block 2 (004000-005FFFh) write-protected
WRT3 = Write Protection Block 3
OFF Block 3 (006000-007FFFh) not write-protected
ON Block 3 (006000-007FFFh) write-protected
Register: CONFIG6H @ 0x30000B
WRTB = Boot Block Write Protection bit
OFF Boot Block (000000-0007FFh) not write-protected
ON Boot Block (000000-0007FFh) write-protected
WRTC = Configuration Register Write Protection bit
OFF Configuration registers (300000-3000FFh) not write-protected
ON Configuration registers (300000-3000FFh) write-protected
WRTD = Data EEPROM Write Protection bit
OFF Data EEPROM not write-protected
ON Data EEPROM write-protected
Register: CONFIG7L @ 0x30000C
EBTR0 = Table Read Protection Block 0
OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks
EBTR1 = Table Read Protection Block 1
OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR2 = Table Read Protection Block 2
OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR3 = Table Read Protection Block 3
OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks
Register: CONFIG7H @ 0x30000D
EBTRB = Boot Block Table Read Protection bit
OFF Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
ON Boot Block (000000-0007FFh) protected from table reads executed in other blocks
Register: IDLOC0 @ 0x200000
Register: IDLOC1 @ 0x200001
Register: IDLOC2 @ 0x200002
Register: IDLOC3 @ 0x200003
Register: IDLOC4 @ 0x200004
Register: IDLOC5 @ 0x200005
Register: IDLOC6 @ 0x200006
Register: IDLOC7 @ 0x200007I got a little (if not much), confused by the difference in the config bits setting from MPLAB v8.63 to v8.83.
It comes all down to me, and my lack of reading...
It comes all down to me, and my lack of reading...
I know.
Why didn't they include usart.h and usart.c for the PIC18, like they did for the PIC16?
Are you supposed to make one yourself?
It in there just dig in more
It's to big to post
all of it.
Here where to look if on C:\Program Files\HI-TECH Software\PICC-18\9.80\sources\plib\USART
Rich (BB code):
#ifndef __USART_H
#define __USART_H
/******************************************************************************
// * USART PERIPHERAL LIBRARY HEADER FILE
******************************************************************************
* FileName: usart.h
* Dependencies: See include below
* Processor: PIC18
* Compiler: MCC18
* Company: Microchip Technology, Inc.
*
* Software License Agreement
* The software supplied herewith by Microchip Technology Incorporated
* (the “Company”) for its PICmicro® Microcontroller is intended and
* supplied to you, the Company’s customer, for use solely and
* exclusively on Microchip PICmicro Microcontroller products. The
* software is owned by the Company and/or its supplier, and is
* protected under applicable copyright laws. All rights are reserved.
* Any use in violation of the foregoing restrictions may subject the
* user to criminal sanctions under applicable laws, as well as to
* civil liability for the breach of the terms and conditions of this
* license.
*
* THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
* TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
* IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*****************************************************************************/
#include <pconfig.h>
/* PIC18 USART peripheral libraries. */
/* There are three library modules, corresponding to register names:
* USART1 (TXSTA1, RCSTA1, etc.)
* USART2 (TXSTA2, RCSTA2, etc.)
* USART (TXSTA, RCSTA, etc.)
* Each module is defined only for those devices for which the register
* names are defined.
*/
/* Corresponding to each module, there are several routines:
*
* The 'open' routine takes two parameters:
* - 'config' is the bitwise 'and' of the appropriate configuration
* bit masks (defined below);
* - 'spbrg' is the baud rate.
* The registers associated with the USART module are set according to these
* parameters; then, the transmitter and receiver are enabled.
*
* The 'datardy' routine returns 1 if data has been received, 0 otherwise.
*
* The 'read' routine returns the received byte. It also sets the framing
* and overrun error status bits (FRAME_ERROR & OVERRUN_ERROR) if necessary;
* also, the status receive bit 8 (RX_NINE) is significant if 9-bit mode
* is enabled.
* (See status bit structure definition below).
*
* The 'write' routine accepts the byte to transmit. If 9-bit mode is
* enabled, the status trasmit bit 8 (TX_NINE) is also trasmitted.
*
* The 'gets' routine accepts a buffer and the buffer length in bytes as
* parameters. It fills the buffer with bytes as they are received; it will
* wait for data if necessary in order to fill the entire buffer.
*
* The 'puts' routine accepts a null-terminated byte string. All bytes
* are transmitted, including the null character. It will wait until the
* USART is not busy in order to transmit all the bytes.
*
* The 'putrs' routine is identical to 'puts', except the byte string
* resides in ROM.
*
* The 'close' routine disables the receiver, the transmitter, and the
* interrupts for both.
*
* The 'busy' routine returns 1 if the transmit shift register is not empty;
* otherwise, it returns 0.
*
* For devices with enhanced USART capability, an additional 'baud'
* routine is provided. This routine takes a 'config' parameter, which
* is a bitwise 'and' of the baud configuration bit masks (see below).
* The BAUDCON (a.k.a. BAUDCTL) register is configured appropriately.
*/
/* Change this to near if building small memory model versions of
* the libraries. */
#define MEM_MODEL
/* Configuration bit masks to be 'anded' together and passed as the 'config'
* parameter to the 'open' routine. */
//-----------AND OR MASK-------------------------------------------------
#ifndef USE_OR_MASKS
#define USART_TX_INT_ON 0b11111111 // Transmit interrupt on
#define USART_TX_INT_OFF 0b01111111 // Transmit interrupt off
#define USART_RX_INT_ON 0b11111111 // Receive interrupt on
#define USART_RX_INT_OFF 0b10111111 // Receive interrupt off
#define USART_BRGH_HIGH 0b11111111 // High baud rate
#define USART_BRGH_LOW 0b11101111 // Low baud rate
#define USART_CONT_RX 0b11111111 // Continuous reception
#define USART_SINGLE_RX 0b11110111 // Single reception
#define USART_SYNC_MASTER 0b11111111 // Synchrounous master mode
#define USART_SYNC_SLAVE 0b11111011 // Synchrounous slave mode
#define USART_NINE_BIT 0b11111111 // 9-bit data
#define USART_EIGHT_BIT 0b11111101 // 8-bit data
#define USART_SYNCH_MODE 0b11111111 // Synchronous mode
#define USART_ASYNCH_MODE 0b11111110 // Asynchronous mode
#define USART_ADDEN_ON 0b11111111 // Enables address detection
#define USART_ADDEN_OFF 0b11011111 // Disables address detection
//------------AND MASK------------------------------------------------
#else
#define USART_TX_INT_ON 0b10000000 // Transmit interrupt on
#define USART_TX_INT_OFF 0b00000000 // Transmit interrupt off
#define USART_TX_INT_MASK (~USART_TX_INT_ON) //Mask Trnasmit Interrupt select bit
#define USART_RX_INT_ON 0b01000000 // Receive interrupt on
#define USART_RX_INT_OFF 0b00000000 // Receive interrupt off
#define USART_RX_INT_MASK (~USART_RX_INT_ON) //Mask Receive Interrupt select bit
#define USART_ADDEN_ON 0b00100000 // Enables address detection
#define USART_ADDEN_OFF 0b00000000 // Disables address detection
#define USART_ADDEN_MASK (~USART_ADDEN_ON) //Mask address detection select bit
#define USART_BRGH_HIGH 0b00010000 // High baud rate
#define USART_BRGH_LOW 0b00000000 // Low baud rate
#define USART_BRGH_MASK (~USART_BRGH_HIGH) //Mask baud rate select bit
#define USART_CONT_RX 0b00001000 // Continuous reception
#define USART_SINGLE_RX 0b00000000 // Single reception
#define USART_CONT_RX_MASK (~USART_CONT_RX) //Mask Continuous Reception select bit
#define USART_SYNC_MASTER 0b00000100 // Synchrounous master mode
#define USART_SYNC_SLAVE 0b00000000 // Synchrounous slave mode
#define USART_SYNC_MASK (~USART_SYNC_MASTER) //Mask usart mode select bit
#define USART_NINE_BIT 0b00000010 // 9-bit data
#define USART_EIGHT_BIT 0b00000000 // 8-bit data
#define USART_BIT_MASK (~USART_NINE_BIT) //Mask 9 bit transmit select bit
#define USART_SYNCH_MODE 0b00000001 // Synchronous mode
#define USART_ASYNCH_MODE 0b00000000 // Asynchronous mode
#define USART_MODE_MASK (~USART_SYNCH_MODE) //Mask sync/async mode select bit
#endif
/* These devices have enhanced USARTs. */
#if defined (EAUSART_V3 ) ||defined (EAUSART_V4 ) ||defined (EAUSART_V5 )||\
defined (EAUSART_V6 ) ||defined (EAUSART_V7 ) ||defined (EAUSART_V8 ) ||\
defined (EAUSART_V9 ) ||defined (EAUSART_V10 ) || defined (EAUSART_V11)
/* The baud configuration bit masks to be 'anded' together and passed to
* the 'baud' routine. */
//--------------AND OR MASK------------------------------
#ifndef USE_OR_MASKS
#define BAUD_IDLE_CLK_HIGH 0b11111111 // idle state for clock is a high level
#define BAUD_IDLE_CLK_LOW 0b11101111 // idle state for clock is a low level
#define BAUD_16_BIT_RATE 0b11111111 // 16-bit baud generation rate
#define BAUD_8_BIT_RATE 0b11110111 // 8-bit baud generation rate
#define BAUD_WAKEUP_ON 0b11111111 // RX pin monitored
#define BAUD_WAKEUP_OFF 0b11111101 // RX pin not monitored
#define BAUD_AUTO_ON 0b11111111 // auto baud rate measurement enabled
#define BAUD_AUTO_OFF 0b11111110 // auto baud rate measurement disabled
//-----------------AND MASK-------------------------------
#else
#define BAUD_IDLE_CLK_HIGH 0b00010000 // idle state for clock is a high level
#define BAUD_IDLE_CLK_LOW 0b00000000 // idle state for clock is a low level
#define BAUD_IDLE_CLK_MASK (~BAUD_IDLE_CLK_HIGH) //Mask Idle Clock State bit
#define BAUD_16_BIT_RATE 0b00001000 // 16-bit baud generation rate
#define BAUD_8_BIT_RATE 0b00000000 // 8-bit baud generation rate
#define BAUD_BIT_RATE (~BAUD_16_BIT_RATE) //Mask 16 bit baud rate select bit
#define BAUD_WAKEUP_ON 0b00000010 // RX pin monitored
#define BAUD_WAKEUP_OFF 0b00000000 // RX pin not monitored
#define BAUD_WAKEUP_MASK (~BAUD_WAKEUP_ON) //Mask Wake-up Enable bit
#define BAUD_AUTO_ON 0b00000001 // auto baud rate measurement enabled
#define BAUD_AUTO_OFF 0b00000000 // auto baud rate measurement disabled
#define BAUD_AUTO_MASK (~BAUD_AUTO_ON) //Mask Auto-Baud Detect Enable bit
#endif
#endif
/* Only these devices have two usart modules: USART1 & USART2. */
#if defined (AUSART_V2) ||defined (EAUSART_V6) ||defined (EAUSART_V7) ||\
defined (EAUSART_V8) ||defined (EAUSART_V9) || defined (EAUSART_V10) ||\
defined (EAUSART_V11)
/* ***** USART1 ***** */all of it.
Here where to look if on C:\Program Files\HI-TECH Software\PICC-18\9.80\sources\plib\USART
Last edited:
I saw that one, but got a little confused when it says MCC18 compiler.
Will it work for the Hi Tech C compiler?
Will it work for the Hi Tech C compiler?
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