I am curious about a strange effect i observed in firmware for a prototype. Here's the quick version of my story:
I will use an 8x5 LED matrix in row x collumn configuration to demonstrate the basis of the operation of POV clocks: the changes of each pixel are too fast for our eyes.
PortB connects to 8 leds of each collumn.Port A selects which collumn will be on.
so, on to the problem:
I set up all of portb as output, all of porta as output, timer1 to active, CCP register to trigger interrupt accurately at ((1/60hz) * 5) = 3333 us = 3333 instruction cycles on timer1 without prescaler.
every time the interrupt triggers, an output routine will emit some value(current line) stored in ram through the index register and then increment the FSR(next line). after incrementing and outputting 5 times, it goes back to the first value . After doing this cycle 30 times(0.5 second), it changes to 5 other values and goes on.
Now, simulating on MPLAB the value of portB and the value fetched on RAM (somewhere between 0x40 and 0x4F) do not match!
So, under advice of another user of the forum,i Disabled the CCP module and Timer1 and used Timer2's overflow interrupt to count time instead.
With timer2 as a timebase instead of timer1 and CCP, the Values Of portB and the lines fetched by the index register started to match!
Something is terribly wrong in the implementation of timer1 and/or CCP1. What might i have missed?could it be a simulation issue?
Check my source code below and see what could have caused the discrepancy of portB.
The zip contains the source code using timer1; The asm contains the updated source using timer2.
I will use an 8x5 LED matrix in row x collumn configuration to demonstrate the basis of the operation of POV clocks: the changes of each pixel are too fast for our eyes.
PortB connects to 8 leds of each collumn.Port A selects which collumn will be on.
so, on to the problem:
I set up all of portb as output, all of porta as output, timer1 to active, CCP register to trigger interrupt accurately at ((1/60hz) * 5) = 3333 us = 3333 instruction cycles on timer1 without prescaler.
every time the interrupt triggers, an output routine will emit some value(current line) stored in ram through the index register and then increment the FSR(next line). after incrementing and outputting 5 times, it goes back to the first value . After doing this cycle 30 times(0.5 second), it changes to 5 other values and goes on.
Now, simulating on MPLAB the value of portB and the value fetched on RAM (somewhere between 0x40 and 0x4F) do not match!
So, under advice of another user of the forum,i Disabled the CCP module and Timer1 and used Timer2's overflow interrupt to count time instead.
With timer2 as a timebase instead of timer1 and CCP, the Values Of portB and the lines fetched by the index register started to match!
Something is terribly wrong in the implementation of timer1 and/or CCP1. What might i have missed?could it be a simulation issue?
Check my source code below and see what could have caused the discrepancy of portB.
The zip contains the source code using timer1; The asm contains the updated source using timer2.
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