Hi,

I'm looking at amplifier behavior for different loads. In LTSpice I made a simulation of an audio amplifier (attached schematic) with a capacitor load of 100nF. I was expecting that the output voltage (yellow waveform/circle on schematic) across the capacitor would lag behind the output voltage (blue waveform/circle) of the voltage amplification stage.

In the plot these voltages are shown, including the current flowing (green waveform/arrow in schematic) in and out of the capacitor and the gate source voltage (red waveform/circles in schematic) of the N-FET (U2). Clearly it is seen that the gate source voltage on this N-FET (U2) leads the output voltage and is maximum when the output voltage is zero. But why is the gate source voltage of this N-FET maximum at this point and why there is no phase lag of the output voltage? Probably there is an error in my thinking. Appreciate any help.

 

I'm not sure if I understand you correctly. How can it be any phase shift between N-FET source voltage and voltage across capacitor ?
If N-FET source voltage is equal to capacitor voltage and N-FET work as a voltage follower . Also do not forget about R12 and R15 and N-FET input capacitance. At firs try R12 = R15 = 10Ω and see the result.

 

What my question basically comes down to is that I would expect that the voltage on the load capacitance would lag behind the output voltage of the voltage amplification stage (blue circle in schematic). However from the plots it can be seen they are in phase (blue and yellow waveform)?

 

What my question basically comes down to is that I would expect that the voltage on the load capacitance would lag behind the output voltage of the voltage amplification stage (blue circle in schematic). However from the plots it can be seen they are in phase (blue and yellow waveform)?

There probably is some phase shift from the blue circle to the red ones. It is just very small.

 

The voltage on the load capacitor IS the amp output voltage. They're the same point. Put a resistor between them & then you'll see some lag (plus filtering of course).

 

What my question basically comes down to is that I would expect that the voltage on the load capacitance would lag behind the output voltage of the voltage amplification stage (blue circle in schematic).

You will not see any lagging because the output push-pull stage is a low impedance stage and can easily provide current needed to quickly charge/discharge the capacitor. And in capacitor the voltage voltage lags the current. Also between the VAS and the Output stage you have an voltage follower.
So you will see no phase shift at "low frequency".

 

Thank you all for the answers, I understand it now. One other question I have is why we don't see the 90 degrees phase shift (caused by the compensation capacitor C6) at the output of the amplifier. Thanks

 

Do you know anything about negative feedback and how the negative feedback change/affects the amplifier frequency response? Also you must distinguish between open loop frequency response and closed loop frequency response.

 

Yes I mean in the situation when in closed loop. In open loop the 90 degree phase shift from the compensation capacitor can be seen an the output, but not in closed-loop. I wonder why that is?

 

Because the negative feedback after we closed-loop increase the amplifier bandwidth .
http://www.allaboutcircuits.com/tec...t-2-improving-gain-sensitivity-and-bandwidth/

 

The bandwidth increases, I agree with you. I am confused because of the following quote from a book on audio amplifiers:

"In real circuits there will be many poles, but if the roll-off behavior is strongly dominated by a single pole, the stability criteria will be more straightforward to meet. The effects of all other poles can then be lumped together as so-called excess phase. In this case, at the frequency where the gain around the loop has fallen to 0 dB, the phase lag of the dominant pole will be 90 degrees."

So it says (in closed loop) when loop gain is unity then the phase lag of the dominant pole caused by the compensation capacitor is 90 degrees and gives us 90 degrees phase margin. But this 90 degrees phase shift doesn't show on the output, the input and output voltage are in phase?
I would expect to see a 90 degree phase shift between in- and output voltage?

 

Have you try to plot frequency response for your amplifier ?

 

Sorry for my late response. Yes I've made a plot from the closed loop gain frequency response. And there it doesn't show the contribution of the dominant pole anymore. This is where i get confused. The dominant pole is there to let the internal open loop gain fall down, so when the loop gain is 0 dB we have enough phase margin to ensure stability. In the theoretical case that the other poles would be far away we have 90 degrees phase margin with dominant pole compensation when the loop gain is 0dB. It means that there is a 90 degree phase shift in the forward path. But at the same time we don't see this 90 degrees anymore when the loop is closed?