Here is my task:
Calculate and sketch output voltage diagram if input signal is Vin = 3sin(3140t). Capacitor has not acumulated energy at beginning.



If we assume that diode doesn't conduct, vout(t) is zero. If it conducts, we model it with 0.7V voltage drop:


It must be id(t) > 0, for our assumption to be correct.
I stuck there. We have one DC (0.7V voltage drop model) and one AC source so it is neccessary to apply superposition, right?

 

If you want. But how about just asking what will happen if the voltage on the capacitor is, say, 1V and the input is at 2V. Then ask what will happen if the voltage on the capacitor is 2V and the input is at 1V.

 

If those are two op amps with negative feedback, then you know that the high open loop gain of the op amp will cause an output that will be such as to try to maintain its "-" input essentially the same as the "+" input (whenever possible i.e. as long as the diode doesn't prevent it).

From that you can readily determine the Vout versus Vin.
It doesn't require any calculations.
This assumes there is no output current limiting by the op amp during operation.

 

The capacitor voltage will follow the input voltage at 0.7V less as long as the input voltage is increasing. When the input voltage decreases, the capacitor stays at the last max (Vin-0.7).

The currents will essentially instantly charge the capacitor as the input voltage increases. In reality there is some lag because of op-amp max current output and diode capacitance and capacitor charge integration time, but these are all small and I assume negligible for this exercise because they'll be off the scale of whatever graph you have to make.

Also, note that the second op-amp is a unity-gain buffer configuration so it just follows the voltage on the capacitor.

There will be some discharge from the capacitor through self-discharge and small input bias currents on the op amps, but I assume both will be negligible for this exercise.

 

The capacitor voltage will follow the input voltage at 0.7V less as long as the input voltage is increasing. When the input voltage decreases, the capacitor stays at the last max (Vin-0.7).

Think about this.

Do what I suggested the TS do. Or, more to the point, assume that the circuit behaves as you describe. Let Vin be 1.7 V and assume that the capacitor voltage will be 1.0 V. What is the differential input voltage to the opamp?

 

The capacitor voltage will follow the input voltage at 0.7V less as long as the input voltage is increasing. When the input voltage decreases, the capacitor stays at the last max (Vin-0.7).
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That is incorrect due to the feedback from the output to the op amp "-" input.
Remember that feedback always tries to keep the "+" and "-" inputs at the same voltage.

 

And if we know that for ideal OPAMP currents through inverting and noninverting inputs are zero, what is purpose of 10k resistances?

 

And if we know that for ideal OPAMP currents through inverting and noninverting inputs are zero, what is purpose of 10k resistances?

Because real opamps aren't ideal.

 

And if we know that for ideal OPAMP currents through inverting and noninverting inputs are zero, what is purpose of 10k resistances?

I see no particular reason or purpose for those resistors in this circuit.

 

That is incorrect due to the feedback from the output to the op amp "-" input.
Remember that feedback always tries to keep the "+" and "-" inputs at the same voltage.

So the + input, when it goes higher than what's on the capacitor and on the - input, drives the output high, and increases the charge (and therefore the voltage) on the capacitor until it equals the + input. So the capacitor will follow the + input but not with a lower offset as I originally said. The high gain of the op-amp overcomes the diode voltage drop to force the capacitor voltage to rise to the level of the + input. So the capacitor should follow the + input exactly (as long as it increases greater than the current voltage on the capacitor).

Is this what you were getting at?

 

Here is my attempt:




vout(t) = vc(t) = 3V.

This was only for one period of input signal.
When input signal start increasing, what will happen?

 

It only matters if the input signal rises above the voltage stored on the capacitor (which will tend to decay with time, but if the leakage currents and bias currents are small, that probably won't be noticeable on the time scales you are dealing with).