I am running SERDES simulations in HyperLynx. I am using IBIS AMI simulations models of Xilinx UltraScale GTH. I am working with transmission line models suitable for PCIe Gen3/Gen4. The eye opening requirement and the BER is shown in attached table.
PCIe Gen3: 0.3 UI, 25 mV, BER of 10-12
PCIe Gen4: 0.3 UI, 15 mV (RX eye spec. is actually 14 mV), BER of 10-12
It look like if a board layout is failing to be compliant with PCIe Gen3, it can be compliant with PCIe Gen4 ? because the eye opening requirement is 15 mV instead 25 mV.
PCIe Gen3: 0.3 UI, 25 mV, BER of 10-12
PCIe Gen4: 0.3 UI, 15 mV (RX eye spec. is actually 14 mV), BER of 10-12
It look like if a board layout is failing to be compliant with PCIe Gen3, it can be compliant with PCIe Gen4 ? because the eye opening requirement is 15 mV instead 25 mV.
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