Hi,
Being a novice in both digital circuits and Logisim, I have a challenge in solving a self made assignment where I try to combine a parity check with a counter. Somehow the counting seems to be out of sync with the clock. I don't want a solution, but rather be pointed in the right direction where to look for the knowledge needed to solve my issue.

CA : Not counting consecutive highs, but only changes from low to high
CB : Counting correct numbers of highs, but on the falling edge after a high
CC : Counting correct numbers of highs, but only on the rising edge of the next cycle

What I'm trying to achieve is to make it count correctly on the rising edge on the right cycle.

Ulf

 

What is the inverter/buffer symbols with the side input? Is that an output enable or a tristate part?

You are implementing gated clocks, which is very difficult to do correctly.

What would help the most would be two timing diagrams. The first one would illustrate what you want to have happen, and the second would illustrate what you are currently seeing that is not correct.

 

I try to combine a parity check with a counter

What is a "parity counter"?

 

What is a "parity counter"?

Sorry for the lack of clarity of purpose. What I'm trying to achieve is to check the parity of 8 bits. If the parity is even, then it should increase the counter by one and if it is odd, it shouldn`affect the counter. The component checking the parity gets its 8 bits data from a random generator.

 

Sorry for the lack of clarity of purpose.

I still can't understand what you're trying to do.

If you want a counter to increment when parity of your random number is even, why aren't you using the output of the parity checker to clock the counter?

Assuming the Clk signal in 3 places is the same signal, the output of the parity checker will occur after the rising edge of clock. That means the counters can't be clocked by the edge that generated the signal to enable the tri-state buffer/inverter.

 

What is the inverter/buffer symbols with the side input? Is that an output enable or a tristate part?

You are implementing gated clocks, which is very difficult to do correctly.

What would help the most would be two timing diagrams. The first one would illustrate what you want to have happen, and the second would illustrate what you are currently seeing that is not correct.

According to Logisim's manual, it should be a controlled inverter. The idea was to try to "reset" the high between two consecutive even parities, hence the use of the inverter. I see you point in making a timing diagram and I will try to do so.

Thanks.