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Parasitic capacitance

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prescott2006

Joined Nov 8, 2008
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I am designing a square root circuit by using Mentor Graphic software. As can seen from the attached figure, I want to ask why is the lower waveform is smoother than the upper waveform? The upper waveform is pre-simulation result and lower waveform is after layout has been interconnect. Don't the parasitic capacitance should deteriorate the waveform?:confused:
 

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