Hi,
Just designing a simple PISO logic design. I already built it and is working fine just need a little help on making it work continously.
Inputs:
pardata[7:0]
dataready
clock
Outputs:
serout
ready
Basically 'ready' becomes 1 when it is ready to accept new data, this is done by just a ripple counter counting out 8 bits. Dataready controls whether or not to load parallel data or serialize data.
Problem I have, cannot figure out how to get 'dataready' to become 1 when 'ready' becomes 1. Can I just wire 'ready' to 'dataready'?
Thanks,
RishiD
Just designing a simple PISO logic design. I already built it and is working fine just need a little help on making it work continously.
Inputs:
pardata[7:0]
dataready
clock
Outputs:
serout
ready
Basically 'ready' becomes 1 when it is ready to accept new data, this is done by just a ripple counter counting out 8 bits. Dataready controls whether or not to load parallel data or serialize data.
Problem I have, cannot figure out how to get 'dataready' to become 1 when 'ready' becomes 1. Can I just wire 'ready' to 'dataready'?
Thanks,
RishiD