Hi
I was wondering if anyone has any experimentally observations or insight they can share on reducing the A/D module's clock of period=Tad below the minimum recommended. For example, yesterday I incorrectly calculated the divisor required to satisfy the min.Tad of 75ns for PIC24FV. I was clocking at ~20ns, yet the error was not evident from eyeballing the voltages I was getting back. Based on this, I suspect that only the precision of the lower few bits is compromised, and that there's probably quite a large safety margin building into the 75ns eg. 75ns will be derived from the maximum possible internal stray RCs whereas typical stray RCs may be much lower. Also for simplicity they may only quote the maximum of the minimum Tads for all the various application scenarios, but if you're only using 10bit precision rather than the full 12bit option then perhaps the real min. Tad could be ~35ns.
Any thoughts?
Robin
I was wondering if anyone has any experimentally observations or insight they can share on reducing the A/D module's clock of period=Tad below the minimum recommended. For example, yesterday I incorrectly calculated the divisor required to satisfy the min.Tad of 75ns for PIC24FV. I was clocking at ~20ns, yet the error was not evident from eyeballing the voltages I was getting back. Based on this, I suspect that only the precision of the lower few bits is compromised, and that there's probably quite a large safety margin building into the 75ns eg. 75ns will be derived from the maximum possible internal stray RCs whereas typical stray RCs may be much lower. Also for simplicity they may only quote the maximum of the minimum Tads for all the various application scenarios, but if you're only using 10bit precision rather than the full 12bit option then perhaps the real min. Tad could be ~35ns.
Any thoughts?
Robin