Outage timer question

Thread Starter

metermannd

Joined Oct 25, 2020
472
Another one for the brain trust... not sure if i've asked around about this circuit before.

this is a timer on an early two-way load management device. The purpose is apparently to indicate if the power has been off long enough the NVRAM contents may be suspect (if the code sees an output state change upon restart, it clears the NVRAM rather than risk bad data being available for download.

My question is, what is the purpose of JFET Q7? Why not just connect C37 / R40 directly to pin 8?
 

Attachments

panic mode

Joined Oct 10, 2011
4,864
that IC is built with BJTs, bias current can be as large as 0.25uA so input impedance is on the order of MOhm. FET has higher impedance...

using single RC stage to form delay is simple but... crude. this is commonly used where delay is short (not better than human estimates). for longer periods it is much better to use oscillator and counter. there are plenty of ICs that can monitor rail voltage.
 

joeyd999

Joined Jun 6, 2011
6,204
NVRAM should retain data for more than a decade.
Depends on the implementation.

Older designs used static RAM powered by a battery or capacitor and called it NVRAM.

You could actually buy static RAMs with a built-in battery.

Today, NV usually means flash. Flash wasn't a (general purpose) thing until the 2000s.
 

Thread Starter

metermannd

Joined Oct 25, 2020
472
joeyd999 is correct - in this case, the 'NVRAM' is a pair of HM-6561 SRAMs (256 bytes of 8-bit RAM), fed by a CR2430 battery when power goes out.

There is a second timer on the same board that handles 'blink' outages (less than 2 minutes) which prompts the code to do some housekeeping before forcing a reboot by watchdog.
 
Top