Oscope trigger A and B for testing RAM, ROM read and write signals

Discussion in 'General Electronics Chat' started by SamEricson, May 3, 2015.

  1. SamEricson

    Thread Starter Member

    Apr 25, 2015
    Some Analog Oscilloscopes have two independent triggers for A and B. They are used to for troubleshooting TTL and CMOS logic circuits that have read, write, control enable problems on the logic board. Since the read and write signals are opposite polarity that is why they made analog oscilloscopes using two independent triggering.

    CH#1 goes to the control enable to the RAM, Oscope Trigger B is Positive Polarity slope
    CH#2 goes to the Chip Enable , Oscope Trigger A is Negative Polarity slope
    CH#3 goes to the Read signal to the RAM , Oscope Trigger A is Negative polarity slope
    CH#4 goes to the Write signal to the RAM , Oscope Trigger B is Positive polarity slope

    Read is a logic low
    Write is a logic high

    Have you seen technicians do something like this to troubleshooting TTL/CMOS logic boards? or troubleshooting RAM/ROM read and write faults on logic boards
    Last edited: May 3, 2015
  2. Hypatia's Protege

    Distinguished Member

    Mar 1, 2015
    While I cannot speak for technicians per se, common engineering practice (Re: 'bench' testing of designs) uses a logic analyzer -- Of course, the outlined (TDO) procedure is acceptable so long as the channel and trigger inputs exhibit sufficient bandwidth and the desired test condition is realizable with the relatively limited channel availability -- Perhaps I don't understand your question?:confused:

    Best regards
    absf likes this.
  3. OBW0549

    Well-Known Member

    Mar 2, 2015
    absf likes this.