Good day! I am trying to make a footprint of PIC12F509 with Orcad layout (I am learning to make footprints and started with this), but I cant seem to get the dimensions properly! I was reading the datasheet:
http://ww1.microchip.com/downloads/en/DeviceDoc/41236E.pdf
Page 94 are the dimensions of the PIC in mm.
I have set Orcad layout to mm, and on the down left corner I have the distance. But no matter how much I calculate the pins, it doesnt add up. I am using the soic package, with 3.9 by 4.9mm, I rounded it up to 4 by 5.
Between the pins I have 0.9mm, between the pin centers I have 1.3mm.
One padstack is 0.4mm for the "DRLDWG" and "Drill" layer.
Top and bottom layer padstacks are 0.5mm.
According to the datasheet form left to right including the pins, the distance should be 6.9mm, but that means 1 padstack should be 1.9mm, which makes them too big, unless I make them rectangle?
I dont understand the note in the datasheet that "Pin 1 has to be in the hatched area". Does that means the pins have to be under the processor, or should I make the area of the circuit more and how much?
http://ww1.microchip.com/downloads/en/DeviceDoc/41236E.pdf
Page 94 are the dimensions of the PIC in mm.
I have set Orcad layout to mm, and on the down left corner I have the distance. But no matter how much I calculate the pins, it doesnt add up. I am using the soic package, with 3.9 by 4.9mm, I rounded it up to 4 by 5.
Between the pins I have 0.9mm, between the pin centers I have 1.3mm.
One padstack is 0.4mm for the "DRLDWG" and "Drill" layer.
Top and bottom layer padstacks are 0.5mm.
According to the datasheet form left to right including the pins, the distance should be 6.9mm, but that means 1 padstack should be 1.9mm, which makes them too big, unless I make them rectangle?
I dont understand the note in the datasheet that "Pin 1 has to be in the hatched area". Does that means the pins have to be under the processor, or should I make the area of the circuit more and how much?
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