From what I can find on the web, this flag should get set to 1 after the device has physically transmitted it's payload.

But it isn't, I poll the FIFO_STATUS register but the flag never gets set and I know the data was sent because I have a receiver board that receives the whole packet.

The manual for the device too, has very little to say about TX_EMPTY, this is the only place the field is mentioned:



The flag is set right before I begin a payload transmission.

Anyone here have any experience of this?

 

I am not at home base right now. I will get back to you later today.

 

Just a guess from using other types of devices. The CE might need to toggled after I/O transactions to reset the device internal state to idle for fifo flags to sequence correctly.

 

Just a guess from using other types of devices. The CE might need to toggled after I/O transactions to reset the device internal state to idle for fifo flags to sequence correctly.

Thanks Spook, well on this device it says when we transmit a payload, we must pulse CE for a period > 10 uS, and in my case it gets pulsed for 16 uS and that's about it for transmission it seems.



I'm actually trying to code it so that we only allow a transmission if there isn't one in progress already, or at least have a way to do that should I want to include that ability.

https://cdn.sparkfun.com/assets/3/d/8/5/1/nRF24L01P_Product_Specification_1_0.pdf

 

What's the spacing between the last SPI clock for the TX transaction last byte and CE?
Ok


Maybe too soon?


A quick search says cs_ena_posttrans should be set in the SPI device config for this spacing adjustment

 

This is been awhile and I cannot recall the details of programming the NRF24L01+.
I believe I used the nrf24.c and nrf24.h files which were written for MSP430. Then I created my own called DMI_nrf24.c and DMI_nrf24.h.
Function names -msp- are from the original MSP430 implementation.
(The .h files have been renamed _h.txt to enable posting as an attachment.)

 

Looking at my main program loop, I have a call to doRequest( ) to the slave device.
It is monitoring TX_DS in STATUS.

void doRequest(void)
{
     RX_count = 0;
     HAL_Delay(10);
 
     RF_ready = FALSE;
     msprf24_activate_tx_mode();
     w_tx_payload( strlen(CMD_ID), CMD_RX );
     msprf24_activate_tx();
     HAL_Delay(10);
     
     // monitor transmission
     if ( r_reg(RF24_STATUS) & RF24_TX_DS ) 
     {
       RF_Mode = RF_RX_MODE;
       RF_ready = TRUE;
       RX_count = 0;
       msprf24_activate_rx();
     }
}

 

What's the spacing between the last SPI clock for the TX transaction last byte and CE?
Ok
View attachment 347947

Maybe too soon?
View attachment 347948

A quick search says cs_ena_posttrans should be set in the SPI device config for this spacing adjustment

I will get this info tomorrow, thanks.

 

Looking at my main program loop, I have a call to doRequest( ) to the slave device.
It is monitoring TX_DS in STATUS.

void doRequest(void)
{
     RX_count = 0;
     HAL_Delay(10);

     RF_ready = FALSE;
     msprf24_activate_tx_mode();
     w_tx_payload( strlen(CMD_ID), CMD_RX );
     msprf24_activate_tx();
     HAL_Delay(10);
  
     // monitor transmission
     if ( r_reg(RF24_STATUS) & RF24_TX_DS )
     {
       RF_Mode = RF_RX_MODE;
       RF_ready = TRUE;
       RX_count = 0;
       msprf24_activate_rx();
     }
}

Hmm, I think I've masked that interrupt!!!!

See MASK_TX_DS bit.

This must be my problem

many thanks

 

This is totally resolved.

I had read or thought I had, that the TX_DS interrupt for transmitted packets was only used when auto Ack was enabled for the device. For that reason I was trying to poll the FIFO_STATUS.TX_EMPTY flag as a way to establish when a transmission was done.

But I was wrong, the TX_DS interrupt is always triggered for a completed transmission irrespective of modes and so on. I had it disabled too (there's a mask bit) and so that compounded my confusion.

It's all working now, the transmitter gets an interrupt as soon as the send is complete.

Thanks for your input gents.