1. I have to read Current transformer reading. CT has both +ve & -ve peaks so I have level shifted the value to 2.5V. As in attached circuit.

2. CT has 50Hz waveform & below is my algo.

1. Init adc
2. Init timer 
3. start timer for 1ms
4. take adc reading & store result in array
5. wait while timer set in step 3 expired
6. repeat step 3 to 5 , 20 times for 50Hz 
7. in array check for highest reading. This is the peak reading

3. Attached is my circuit.

4. Problem is there is noise in reading. For same input value i.e CT output, microcontroller reading shows huge variation.
However if I try by connecting external potentiometer reading is stable. So I think no problem on MCU side.

5. Problem is on external circuit. How to remove noise there , can I connect filter capacitor across ac signal??
Cannot add opamp since circuit is cost sensitive.

 

Try eliminating R3 and change R1 and R4 to 1kΩ.

 

The Vout = 2.5Vdc + V1 - VR3.
What is the V1 used for?

 

At 50Hz the entire AC cycle takes just 0.02 seconds so you you sample it 20 times every .001 second to get pieces of the whole waveform.

That sounds reasonable. How large is this "noise" in relation to the signal?

You could try taking more readings. No need to save them all, just start with the largest reading VL=0, and if the next current reading VC is larger then the largest then just reassign it with VL=VC.

I do note you toss away half your range with that scheme. Toss away R1 R4 Ca and C2, connect V1 to circuit ground, and add a schottky diode to ground past R3 to catch the negative side.

 

I had added a 0.1uF cap & I get stable reading now.

@ErnieM:
1. Currently i am sampling at 1Khz for 50Hz signal. What should be sampling rate for best result.

2. I have attached a circuit. Is this how you are saying to connect.
I cannot increase R5 resistor, since it is burden resistor across CT.

3. Will adding 1nF resistor in parallel (in atached ciruit it is mentioned 0.1Uf wrongly), will effect the circuit.
According to me, during +ve half , diode is reverse biased, so RC form a low pass filter. With R=50 ohm & C = 1nF.
Fc = 318Hz

In negative half, diode will be forward biased & clip the negative half.
However 10BQ015 have Vf = .21V. So voltage during -ve half will be -0.21V.
This may create issue

 

Do you get the same noise with the CT input disconnected? This test would tell you a great deal.

The other approach is to remove all the capacitors entirely, since the ADC is ratiometric to the Vdd supply, (is it? no fixed reference?) adding the capacitors creates phase shifts between the Vdd noise and the 1/2 Vdd node, this makes the Vdd noise appear in the ADC signal, basically you are reading a capacitor with a stable voltage with an ADC referenced to the ever noisy Vdd.

Reduce the value of R1 and R4 to lower the impedance of this node for sure.

 

1. Currently i am sampling at 1Khz for 50Hz signal. What should be sampling rate for best result.

For the "best" result you need an infinitely high sample rate.

For the real world you have to work off your error budget. A sine wave at the peak is changing slowly, so you need to compute the max delta V from the peak you can tollerate, then convert that into a time.

Once you have that number you can figure out the sample rate to always hit within that window.

2. I have attached a circuit. Is this how you are saying to connect.
I cannot increase R5 resistor, since it is burden resistor across CT.

Not quite. Sorry I can't make a sketch today. Place R5 parallel to the V2 source, ground one end. Then connect the other end thru R3 1K resistor to D1.

3. Will adding 1nF resistor in parallel (in atached ciruit it is mentioned 0.1Uf wrongly), will effect the circuit.
According to me, during +ve half , diode is reverse biased, so RC form a low pass filter. With R=50 ohm & C = 1nF.
Fc = 318Hz

Unknown (by me... other may know).

In negative half, diode will be forward biased & clip the negative half.
However 10BQ015 have Vf = .21V. So voltage during -ve half will be -0.21V.
This may create issue

Check the data sheet for your device. Typically you're allowed around 0.7V negative on I/O pins.

Heck, I stuck the full AC line voltage into an I/O pin once on a dimmer. True it was isolated by a large resistor, though I didn't even add that diode but used the internal ESD diode to catch and clip the negative side.

I should also ask how stable is the reference to the A2D? Do you have a seperate reference or are you just relying on the Vcc voltage?

 

Thanks @ErnieM,

Schematic as in my post #1, with 0.1uF at input with 1Khz sample i.e 20 times more than input signal freq.
This is working for me