I couldn't resist buying some chips of a new PIC type, the PIC16F1619. This is an "enhanced midrange" unit with a lot of new hardware features and greatly increased speed compared with my existing favorite processor, the PIC16F690, and the pinout is compatible, so I can just replace the processor in existing projects.

All the old assembly instructions seem to be unchanged, so I can continue using the same compiler. However, there are several new instructions which the compiler obviously won't know anything about. My first thought was "I'll just put those into blocks of assembler whenever I think it's worth using them" but then it occurred to me that the assembler won't recognize them either! Now the best I can come up with is some crock involving a #define operation that replaces particular assembly instructions with inline data words, though I'm totally unsure whether that will work.

Here's the data sheet. The chips aren't fully available through vendors yet, but I paid about $1.50 each from Microchip Direct.
http://ww1.microchip.com/downloads/en/DeviceDoc/40001770A.pdf

Example:
The MOVIW instruction moves data from an indirect memory location to W, using either of 2 different memory pointers, with pre- or post- increment or decrement, or with an offset in the range -32 to +31. Sounds like fun!

Any brilliant ideas for making the new features work? I suppose the obvious thing is to get Microchip's own software, but it would be a pain to switch compilers.

 

I have been playing with the 16F1519 for awhile. Had no problems making the new features work using MPLab 8.92.

Here is a working example for putting a calibration value into program memory. It is from a program in development and has not been cleaned up:

;*******************************************************************************
;                          Erase Program Memory
;*******************************************************************************
; Flash memorty must be erased before re-writing.  Cannot just write over it.
; Be sure to load PMADR registers in little endian sequence.
; TzH and TzL are located in shared data memory 0x70 - 0x7F (common RAM)
;*******************************************************************************
ErasePM
     BANKSEL   PMADRL         ;Select bank for PMCON registers               |B3  
     movlw     0xE0      
     MOVWF     PMADRL
     movlw     0x3F        
     MOVWF     PMADRH
     BCF       PMCON1,CFGS    ;Not configuration space
     BSF       PMCON1,FREE    ;Specify an erase operation
     BSF       PMCON1,WREN    ;Enable writes
     MOVLW     55h            ;Start of required sequence to initiate erase
     MOVWF     PMCON2         ;Write 55h
     MOVLW     0AAh
     MOVWF     PMCON2         ;Write AAh
     BSF       PMCON1,WR      ;Set WR bit to begin erase
     NOP                      ;NOP instructions are forced as processor starts
     NOP                      ;row erase of program memory.
     BCF       PMCON1,WREN    ;Disable writes
     movlb     0              ;necessary?                                    |B0    
     return
;*******************************************************************************
;                             PutZero (save calibration to PM)
;*******************************************************************************
PutZero
    BANKSEL   PMADRH          ;Are folllowing steps redundant?                  |B3
     movlw     0x3F  
     MOVWF     PMADRH
     movlw     0xE0
     MOVWF     PMADRL    
     BCF       PMCON1,CFGS    ;Not configuration space PMCON1=80 (after step)
     BSF       PMCON1,WREN    ;Enable writes PMCON1=84 (after step)
     movf      TzL,w          ;Load low byte of Tz register pair
     MOVWF     PMDATL         ;8-bit register
;High byte of data is restricted to 6 bits, however, masking of the two MSB of
;TzH, which are set only for negative offsets, is not necessary.  Rebuilding
;is necessary in GetZero.
     movf      TzH,w
     MOVWF     PMDATH
PM_WRITE
     BCF       PMCON1,LWLO    ;No latches loaded, single word    
     MOVLW     55h            ;Start of required write sequence:
     MOVWF     PMCON2         ;Write 55h
     MOVLW     0AAh      
     MOVWF     PMCON2         ;Write AAh
     BSF       PMCON1,WR      ;Set WR bit to begin write
     NOP                      ;NOP instructions are forced as processor
     NOP                      ;loads program memory write latches
     BCF       PMCON1,WREN    ;Disable memory writes
     movlb     0              ;added 11.18.14                    
     Return

Also attached is a text file of a routine from Mike McLaren (K8LH) for using the stack and some of the new commands for printing.

It was kind of neat to be working in simulation (ICD3) and actually be able to see the program memory change as I injected values. TzL is the register with the calibration value.

John

 

Here's a document from Microchip that describes migration issues to Enhanced Midrange. They took pains to make migration as easy as possible. The two are pretty compatible. Much existing assembler code will run with no changes, even if that means you don't get the use of the enhanced features. A few things like bank selection and indirect addressing are different. If the legacy code uses BANKSEL (as opposed to STATUS,RPx) for example, it should port with little trouble. IRP for the 9th FSR bit will have to be tweaked. I would expect that a C compiler for midrange would have trouble with indirects etc. You'd also have to define all of the SFRs in the banks to fully configure ports etc. Possible to do but...

My personal view is its less trouble to migrate to the correct tools (XC8) than try to coerce old tools to do a new job. I've done some of that and feel its more trouble than its worth.

Just my .02

 

Thanks for the responses. Jpanhalt, I don't see any of the new instructions in your code, but the file you attached certainly has some. I assume "BANKSEL PMADRH " really means load the BSR register.

I'm imagining that the first things I do with the 1619 will involve code that I can test on the PIC16F690 first, and I'll add the unfamiliar features over time. JohnInTX, you're right that a serious difference is going to be bank selection, via the BSR register instead of the top bits of STATUS. I can do #define operations for as many registers as necessary, but if the compiler won't do the bank selection for me (32 banks, ouch!) that seems like a major problem.

I use the Boostc compiler, and one thing I have found is this thread on the forum there:
http://forum.sourceboost.com/index.php?showtopic=5054
It seems to say that the compiler has included the added instructions for literally years. I'll have to investigate that. But it might be that Microchip's output of new processors will run ahead of any company's ability to keep updating compilers, so the XC8 compiler will be the only one that can fully utilize the hardware!

 

Maybe not new instructions per se, but new capabilities. I don't believe that you can directly access program memory in the 16F690 (you do have EEPROM), nor can you directly access the stack. Indirect addressing is enhanced. You have different rotates available, and so forth. My examples were not meant to be exhaustive. What I wanted to point out was that the current version of the compiler, 8.92, has no problems with those instructions. As JohnInTx pointed out, it is not going to interpret a Status, RPx for you into a Banksel. You will see in the disassembly a banksel converted into a movlb. Converting an old program from, say a 12F683 to a 12F1840 is relatively painless.

John