I'm using the above latch in a design. The d input will be zero on power up ,how do I ensure the output will be zero to??

Mod: Added datasheet.

 

If you make LE go high during startup you will achieve it.
Where does your LE signal normally come from?

 

No where at the moment . I guess I can just use an rc reset on it

 

I'm using the above latch in a design. The d input will be zero on power up ,how do I ensure the output will be zero to??

Mod: Added datasheet.

Satisfy the first row of the truth table at power up.

 

In addition to assuring that the input is zero before asserting LE, also make sure that OE is HI

 

In addition to assuring that the input is zero before asserting LE, also make sure that OE is HI

Output is enabled when OE is low.
So keeping OE high during reset and using a pull-down resistor would also work.

 

now thinking of using a reset chip such as the TCM809. for reliability