Hi All,

I have an assignment (below) and do not know where to start??

All I know is that I would like to use a 3 stage with NPN(CE) - PNP(CE) -NPN(CC) but as far as my bias calculations go I am not sure.

HELP please!

PROBLEM
A sensor has a peak open circuit voltage of 1mV with an output resistance of 10k. Design an interface amplifier to allow this sensor to drive a 50 load.
The following constraints are placed on your design.

1. 1. The gain (with load connected) of your amplifier should be 2000 ± 15%
2. 2. The low frequency cut-off should be less than 500Hz.
3. 3. The high frequency cut-off should be greater than 50kHz.
4. 4. The circuit is to be biased from a ±12V DC power supply.
5. 5. The circuit should produce no clipping or distortion in the output voltage waveform when the input voltage is at its maximum value (1mV

1. pk).
   [*]6. You can use any size resistors but your capacitor values can be no larger than 10μ in size.
   [*]7. You can only use NPN 2N3904 or PNP 2N3906 transistors. The parameters for these transistors are;

2N3904  = 150, C = 4.5pF and C = 3.5pF
2N3906  = 150, C = 6.3pF and C = 5.8pF
Note that in real transistors (and indeed in the simulation software) these values will vary depending upon the transistor bias conditions. Use these values in your manual calculations but recognize that when you simulate the circuit you may get slightly different results because of this.
As a challenge you are to minimize the number of transistors used. Marks will be awarded for using less transistors.
As part of the design process you should simulate your circuit and confirm its operation.

 

1. The gain (with load connected) of your amplifier should be 2000 ± 15%

Search google for a two-stage amplifier.

2. The low frequency cut-off should be less than 500Hz.
3. The high frequency cut-off should be greater than 50kHz.

Search google for a low-pass filter.
and Search google for a high-pass filter.

4. The circuit is to be biased from a ±12V DC power supply.

This means hook your circuit to a 12V supply. You can use 8 1.5V cells. Make sure all those cells are connected the same way. Like, don't connect the two button parts (the +ve connection) of your cells together.

5. The circuit should produce no clipping or distortion in the output voltage waveform when the input voltage is at its maximum value

Search google for transistor biasing.

As a challenge you are to minimize the number of transistors used. Marks will be awarded for using less transistors.

It is possible.

 

mik3ca,

One minor correction there. It says +/-12V. You actually need two 12V supplies. One from ground to +12V, the other from ground to -12V.

 

Thanks I have a circuit now.

I am having problems getting a high enough Rin ( I need about 8k or more) on the first stage as my bias current is so big ( required) .I have more than enough gain but my voltage divider on stage 1 is really letting me down. ( Rin/(Rin+Rs)).

I am considering placing a fourth stage (CC) to fix this problem but would prefer to stick with the three.

Any advice on how to keep the stages down to a minimum??

Cheers