Hello, everyone! I have tried attempt my Digital Electronics Assignment which wanted us to do a paper design of an octal-to-7-segment common cathode decoder for digits 0, 2, 5, 6, 7 only using the least possible number of NAND gates (i.e. an optimum design). You are to assume that only octal digits 0, 2, 5, 6, 7 are applied to the inputs of the decoder, i.e. combinations for digits 1, 3 and 4 are never applied.

They gave us a multisim template that we need to use. (ive attach 1) one of my attempts 2) the original template given). Can someone please guide me through on how to completing this assignment? Did I get the first part correct? (number 0).
Our teacher literally just threw the assignment on us without teaching us anything about this... Thank you for helping and have a nice day...having panic attacks right now...not even joking...

 

Welcome to AAC!

Cropped, edited circuit:

Our teacher literally just threw the assignment on us without teaching us anything about this...

For homework, you need to show your work so we can see where you need help.

Saying you weren't taught anything seems suspicious. It's a crude exercise (Multisim has a seven segment display). What have you been taught with respect to truth tables, Kmaps, and connecting gates? Do you see a problem with the way you've connected the outputs of the two NAND gates?

Show us how you arrived at the logic.

You posted two days ago. When is this assignment due?

 

Are you allowed to use diodes?
Do you know how to form an AND from two NAND gates?

Allen