hey people,
i started reading about multiplexers recently and could not understand implementation of logic gates using mux's. I got to know the methodology the way they have implemented certain functions say Ʃm(1,3,5,7,8,9,12) using 4:1 mux with a,b as select lines.
Here they form k-map and get out some boolean expression and apply it to data lines or inputs where the boolean expressions are in form of c,d.
i did not get after this i.e as per my knowledge Ʃm(1,3,5,7,8,9,12) means it's the sop equation and when i am realizing this function i should get out this function as a whole right?? Am i right?? Please help i am unable to understand this point that how exactly is the given sop equation realised......???

 

Too many abbreviations and not enough part numbers. Magic 8 ball says, "Please try again".

 

Too many abbreviations and not enough part numbers. Magic 8 ball says, "Please try again".

To much coffee or tea.

 

Coffee! I make really good coffee.

 

Coffee! I make really good coffee.

Give me a cup of hot coffee ...

Do you think there is something wrong here:
Ʃm(1,3,5,7,8,9,12) using 4:1 mux with a,b as select lines

One selection from four and two selection lines, it means that there are only 8 lines 0~7, where are those 8,9,12 come from?

 

In general, you can implement any logic function of N variables with a 2^N:1 multiplexer. No problem seeing how this is done -- you simply tie each input that corresponds to a term in the SOP expression for the logic function HI and tie all the others LO.

But you can also implement any logic function of N variables using a 2^(N-1):1 multiplexer and a single inverter.

To consider how this is done, focus on the fact that you have one fewer mux control inputs than you have inputs to the logic function. So make a truth table for all of the possible data values that you might have to feed into a given mux data input.