Hi, I am trying to do a spice simulation of a dynamic circuit using PMOS and NMOS. Basically there is an precharge PMOS in series with the N-BLOCK LOGIC consists of the equation /A+BC, which is two parallel NMOS with one of the leg of the parallel has two NMOS in series, then in series with the evaluation NMOS.
I have a vpulse for the clk on the PMOS and the bottom evaluation NMOS. Then I am just testing to see if the output changes with VDD or GND voltages going to the gates of the N-BLOCK LOGIC NMOS gates.
The simulation looks correct for the case where all the NMOS gate inputs are 0V (means turned off), so the output stays high during the precharge and evaluation stage. But when I try to do different combinations on the gate inputs, it gives me pretty much the same result.
Any suggestions?
I have a vpulse for the clk on the PMOS and the bottom evaluation NMOS. Then I am just testing to see if the output changes with VDD or GND voltages going to the gates of the N-BLOCK LOGIC NMOS gates.
The simulation looks correct for the case where all the NMOS gate inputs are 0V (means turned off), so the output stays high during the precharge and evaluation stage. But when I try to do different combinations on the gate inputs, it gives me pretty much the same result.
Any suggestions?