I am setting up a circuit for reading a 10k type 3 thermistor (10kohms). I have an MPC3008 ADC I will be interfacing with an AVR/Atmega644P microcontroller. Why does Microchip recommend higher clock speeds for higher Vdd? I came to believe higher operating voltage allows higher ADC clock speed, but can't understand why it would require it. Or maybe their choice to place table 6-1 next to the paragraph about minimum clock speeds is just confusing me?


The datasheet, regarding SPI clock speed:

"Figure 4-2: Maximum Clock Frequency vs Input resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions." At my input resistance of 10kohms and Vdd of 5V, it shows a clock speed around 0.75 Mohms. I take this to mean if I set SPI clock speed around 0.75 MHz, that will avoid any accuracy issues.


Later in the sheet:

Page 22, Maintaining minimum clock speed: "the time between the end of the sample period and the time that all 10 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz)" (page 22, "maintaining minimum clock speed"). Again, this seems to suggest my clock speed will be fine.

But then this part comes along:

Table 6-1 (page 22): Note 1: 200 ksps is recommended for VDD>=4V Shows recommended clock speed increasing to 3.6MHz with Vdd greater than 4V.



Here is the datasheet:

https://ww1.microchip.com/downloads...ets/MCP3004-MCP3008-Data-Sheet-DS20001295.pdf

 

There is the SAMPLE rate (completed conversion in X time, 200 ksps) and the SPI clock speed (3.6 MHz) needed for the internal circuits to completely (setup time, sample time, hold time, convert time, data buffer time) execute that SAMPLE rate at X voltage.

Maximum Clock Frequency vs Input resistance (RS):
The circuit charges the internal and parasitic capacitance of the sample and hold circuit. It's a RC time constant, lower RS means the capacitance charges to the actual input voltage faster, a higher RS makes it slower. The sample and hold times are set by the SPI clock. So if the RS is high, and the RC time constant is long, you need to increase the sample and hold times by using a slower SPI clock. This is why gain blocks or signal buffers are used to provide a much lower source impedance to the ADC input. This lower RS allows for Max sample rates, with higher SPI clocks, for higher throughput.


As the Vdd decreases, it's typical for internal conversion circuits to need more time for each complete conversion cycle (for various reasons of lower noise margins, charge mobility in semiconductors, etc ..). So the max SAMPLE rate for usable, stable data decreases with lower voltage and to meet the timing for that decrease in the SAMPLE rate, the SPI clock speed needs to decrease because there is a dependency between them.

 

Thank you for the graphic and excellent explanation. I have been studying these concepts for the last 24 hours (very new to this) and think I have a very basic understanding of the reasons behind minimum/maximum clock speed/sample rate. Still, I cant understand what would be wrong with the 0.75Mhz clock speed. I am just a bit confused by table 6-1 which seems to suggest a 3.6MHz clock speed is desirable at higher Vdd.

Are you suggesting the higher sample rate recommendation for > 4V is actually about maximum rather than minimum?

To make things easier for me to understand, does a 0.75Mhz clock speed seem reasonable in this case (so that I may avoid gain blocks/signal buffers yet still achieve good accuracy reading my slowly-changing thermistor reading which my program needs about twice per second)?

 

Yes, sample rates recommendations are maximum. I haven't looked in detail at the datasheet to see if the rate is fixed at the maximum for each clock rate.

The 0.75Mhz clock speed will obviously limit the ADC maximum sample rate and digital interface speed but it might work for your thermistor circuit. How did you decide on using the 0.75Mhz clock speed?

 

Yes, sample rates recommendations are maximum. I haven't looked in detail at the datasheet to see if the rate is fixed at the maximum for each clock rate.

The 0.75Mhz clock speed will obviously limit the ADC maximum sample rate and digital interface speed but it might work for your thermistor circuit. How did you decide on using the 0.75Mhz clock speed?

I chose 0.75MHz based on figure 4-2 showing "Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions." 0.75MHz appears to be the intercept value of the line at 10,000ohms impedance.

 

I chose 0.75MHz based on figure 4-2 showing "Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions." 0.75MHz appears to be the intercept value of the line at 10,000ohms impedance.

What's the sample rate at 0.75MHz? If it's more than you need, that clock can be reduced (don't know what the chips operational min clock rate is) to give more margin for nominal conditions at your desired sample rate.

 

The formula given in the data sheets shows dividing SCLK by 18 gives sample rate. So at 750,000Hz that's a sample rate of ~41,667Hz.

Are there applications where this sample rate is not sufficient? Incredible.

I found this in datasheet which seems to suggest 10KHz minimum: "This means that the time between the end of the sample period and the time that all 10 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz)"

 

The formula given in the data sheets shows dividing SCLK by 18 gives sample rate. So at 750,000Hz that's a sample rate of ~41,667Hz.

Are there applications where this sample rate is not sufficient? Incredible.

Lots of applications where you are digitizing things like audio range signals or have short windows (get several complete samples in the need window) for sampling currents in things like converter circuits.

My cheap oscope has a sample rate of 1G Sa/s as a requirement to see 200MHz input signals.

 

Lots of applications where you are digitizing things like audio range signals or have short windows (get several complete samples in the need window) for sampling currents in thing like converter circuits.

My cheap oscope has a sample rate of 1G Sa/s as a requirement to see 200MHz input signals.

Ah I see. I assume averaging multiple samples is a method of ensuring accuracy?

Appreciate all the help today. Now I can move forward with my design.

 

Ah I see. I assume averaging multiple samples is a method of ensuring accuracy?

Appreciate all the help today. Now I can move forward with my design.

Not necessarily in all conditions. if you average good data (the ADC conversion data matches (to the best extent possible) the actual analog input signal) with random noise it can improve the S/N ratio and maybe deliver improved bits of resolution. If you average bad (bad conversions of input signals) data with no noise, you still get bad data as the result.

You can't polish a turd.