So on advice of @Hypatia's Protege, @theodoravain and I are trying to help newbie comprehension with simulation instead of just formulas alone. But problem is now I'm having trouble understanding Ltspice behavior simulating vry simple circuit!

So here's screen capture of simulation showing ripple voltage from just bridge rectifier fed by 120V(RMS) sine wave with output filtered by LC pi-section loaded by pure resistance. Anyhow what I don't understand is why ripple amplitude is so jittery? Cuz after all, simulation is perfect world w/o anything going on that I didn't draft into circuit?

Here's link LtSpice schematic file

So huge thanks for any help or even just guesses!

PS I know 1N914 is small signal diode not pwr rectifier but Ltspice doesn't enforce those parameters so anything except _default_ diode works for high current or voltage in simulations

 

Hello,

Try to simulate with 1N4007 or 1N540X in stead of the small signal diode 1N914, wich is only good for 300 mA.

Bertus

 

Hello,

Try to simulate with 1N4007 or 1N540X in stead of the small signal diode 1N914, wich is only good for 300 mA.

Bertus

Bertus 1N4007 and 1N540X aren't on Ltspice's list of diode models and I don't know how to create component models from scratch But I totally guarantee it wouldn't make any difference cuz simulator doesn't enforce max characteristics (except o/c PIV for Zeners). But tnx for reply!

 

With the 1N914 you get about 40V forward bias across the diodes. Try MURS120 instead.

 

With the 1N914 you get about 40V forward bias across the diodes. Try MURS120 instead.

AlbertHall Tnx!

That's vry interesting cuz using MURS120 diodes makes definite improvement! So random amplitude pattern is still there but amplitude excursion is way less! So do u think that's just simulation artifact? Or something I'm overlooking?

 

Change the inductor to 12m and it gets really wild.

 

Change the inductor to 12m and it gets really wild.

So with that, ripple is basically like 120Hz _carrier envelope_ modulated by abt 12Hz which is interesting cuz Res freq of 12mH inductor with 15mF cap ≈ 12Hz and o/c 120Hz is the totally expected ripple Freq! So I'm seeing lots of trees but still no sign of the forest!

 

Ok just by juggling L and C components of filter network I can definitely say what's happening is 120Hz ripple freq is being mixed with resonant freq of inductor and output cap! So I can envision ways that could happen in _real world_ but not in perfect noise and parasitic-component free world of simulator?! So ANY ideas are totally welcome! Also plz don't anybody be bashful cuz I guarantee nobody's ideas abt this can be any wilder than mine!

 

but not in perfect noise and parasitic-component free world of simulator

Spice models are not necessarily perfect. Default parasitic resistance, capacitance or inductance values are often assumed so that convergence of the simulation is possible.

 

So here's screen capture of simulation showing ripple voltage from just bridge rectifier fed by 120V(RMS) sine wave with output filtered by LC pi-section loaded by pure resistance. Anyhow what I don't understand is why ripple amplitude is so jittery?

From the waveform you showed, it looks to me like LTSpice is simply not displaying enough samples to create a neat-looking sine wave-- so it looks "jittery."

This is very common in SPICE simulations when the simulator is allowed to take excessively large time steps when simulating the circuit, or when too long a data sample interval is chosen. It looks to me like one or both of these is out of whack, causing LTSpice to not display a smooth waveform.

I don't use LTSpice (I use an older SPICE package, ICAPS4 from Intusoft) so I don't know the particulars of how to adjust these simulation parameters in LTSpice. But as in ICAPS4, it should be pretty easy; it's probably in some menu or dialog box somewhere. I would suggest reducing both parameters by a factor of 10 to start with. Perhaps one of our LTSpice gurus can step in and show you how.

Don't bother fiddling with component values; that's not where the problem lies.

 

I used to repair large DC supplies regulated by SCRs on the primary and smoothed by just that style of filter. They had a resistor connected across the inductor. Maybe now I know why? Try 1Ω.

 

Read section 6 here: http://www.designers-guide.org/Design/bypassing.pdf

 

Instead of applying a rectified sinusoid to the filter, hit it with a singe rising edge of 100 V via a diode (so it is not loaded by the source) and see how long the filter takes to ring down to steady state. You are looking at ripple of about 0.7 V peak to peak, including the "jitter" and the latter is about 0.2 V of that, or about 0.2% of the average voltage.

Also do a frequency response plot for the filter and load (i.e. AC input to the filter).

These should give you some clues.

 

This is very common in SPICE simulations when the simulator is allowed to take excessively large time steps when simulating the circuit

Reducing the maximum time-step to 1uS (Simulate/Edit Simulation Cmd) eliminates the oddities in the ripple, once the circuit has stabilised.

 

Reducing the maximum time-step to 1uS (Simulate/Edit Simulation Cmd) eliminates the oddities in the ripple, once the circuit has stabilised.

But all that wiggliness will still be triggered by transient load conditions in the real world.

 

Everybody huge thanks for help! Sry for late response! Just so u know this is first time I've been on since my last post! Anyhow I'll definitely give post by post responses ASAP!

 

See